ADL5240ACPZ-R7 datasheet(22/28 Pages) AD

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ADL5240

Data Sheet

Rev. A | Page 22 of 28

AMPLIFIER DRIVE LEVEL FOR OPTIMUM ACLR

It is usually required to drive the amplifier as high as possible in

order to maximize output power.However, properly driving

Amplifier at the ADL5240 is required to achieve optimum

ACLR performance. Once output powerapproaches P1dB and

OIP3, there is ACLR degradation. Thedriving level of amplifier

with a modulated signal should bebacked off properly from

P1dB by at least the amount of a signal crest factor for optimum

ACLR. So assuming a gain and output P1dB of Amplifier at

2140 MHzare 19 dB and 19 dBm respectively, the output

power, which is backed off by 11 dB crest factor at the

modulated signal case, is 8 dBm. Therefore, theproperinput

driving level should be under −11 dBm.

–90

–30

–40

–50

–60

–70

–80

–40

–35

–30

–25

–20

–15

–10

–5

PIN (dBm)

AMP_ADJ

AMP_ALT

Figure 39. Single Carrier WCDMA Adjacent Chanel Power Ratio vs. Input

Power at Amplifier, 2140 MHz

THERMAL CONSIDERATIONS

The ADL5240 is packaged in a thermallyefficient,5 mm× 5 mm,

32-lead LFCSP. The thermal resistance from junction to air (θJA)

is 36.8oC/W. Thethermal resistancefor theproduct wasextracted

assuming a standard 4-layerJEDEC board with 25 conductive,

epoxy filled thermal vias. The thermal resistance fromjunction

to case (θJC) is 6.9oC/W, where case is the exposed padof the

lead frame package.

The ADL5240 consumesapproximately 93 mAwitha 5 V supply

voltage. Even though the part dissipates lessthan 0.5 W, for the

best thermal performance, it is recommended to add as many

thermal vias as possible underthe exposedpad of the LFCSP.

The thermal resistancevaluesgiven in this section assume a

minimum of 25 thermal vias arranged in a 5 × 5 array with a

diameter of 13 mils and a pitch of 25 mils. Figure 40 shows a

close-up of thethermal via distribution undertheexposedpad.

Figure 40. Exposed Pad with Thermal Via Distribution

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