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HMC674LC3CTR-R5 数据表(PDF) 5 Page - Analog Devices

部件名 HMC674LC3CTR-R5
功能描述  9.3 GHz Latched Comparator
PDF  14 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

HMC674LC3CTR-R5 数据表(HTML) 5 Page - Analog Devices

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Data Sheet
HMC674LC3C/HMC674LP3E
Rev. K | Page 5 of 14
TIMING DESCRIPTIONS
Table 6.
Parameter
Symbol
Description
Input to Output High Delay
tPDH
The propagation delay measured from the time the input signal crosses the reference
(± the input offset voltage) to the 50% point of an output low to high transition.
Input to Output Low Delay
tPDL
The propagation delay measured from the time the input signal crosses the reference
(± the input offset voltage) to the 50% point of an output high to low transition.
Latch Enable (LE/LE) to Output High Delay
tPLOH
The propagation delay measured from the 50% point of the latch enable (LE/LE)
signal high to low transition to the 50% point of an output low to high transition.
Latch Enable (LE/LE) to Output Low Delay
tPLOL
The propagation delay measured from the 50% point of the latch enable (LE/LE)
signal high to low transition to the 50% point of an output high to low transition.
Minimum Hold Time
tH
The minimum time after the positive transition of the latch enable (LE/LE) signal
that the input signal must remain unchanged to be acquired and held at the outputs.
Minimum Latch Enable (LE/LE) Pulse Width
tPL
The minimum time that the latch enable (LE/LE) signal must be low to acquire an
input signal change.
Minimum Setup Time
tS
The minimum time before the positive transition of the latch enable (LE/LE) signal
that an input signal change must be present to be acquired and held at the outputs.
Output Rise Time
tR
The amount of time required to transition from a low to a high output as measured
at the 20% and 80% points.
Output Fall Time
tF
The amount of time required to transition from a high to a low output as measured
at the 20% and 80% points.
Input Overdrive Voltage
VOD
The difference between the input voltages (VINP and VINN).
Timing Diagram
LATCH ENABLE (LE)
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE (LE)
Q OUTPUT
Q OUTPUT
LATCH
TRACK
LATCH
LATCH
50%
50%
50%
VCM ± VOS
TRACK
tH
VIN
VOD
tF
tS
tPL
tPDL
tPDH
tPLOH
tPLOL
tR
Figure 2. Timing Diagram



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