HMC674LC3CTR-R5 datasheet(7/14 Pages) AD

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Data Sheet

HMC674LC3C/HMC674LP3E

Rev. K | Page 7 of 14

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VTP

INP

INN

VTN

VCCO

VEE

PACKAGE

BASE

NOTES

1. NIC = NOT INTERNALLY CONNECTED. CONNECT

THIS PIN TO GROUND FOR IMPROVED NOISE.

2. EXPOSED PAD. THE EXPOSED PAD MUST BE

CONNECTED TO VEE.

HMC674LC3C

TOP VIEW

(Not to Scale)

Figure 3. HMC674LC3C Pin Configuration

VTP

INP

INN

VTN

VCCO

HMC674LP3E

TOP VIEW

(Not to Scale)

VEE

PACKAGE

BASE

NOTES

1. NIC = NOT INTERNALLY CONNECTED. CONNECT

THIS PIN TO GROUND FOR IMPROVED NOISE.

2. EXPOSED PAD. THE EXPOSED PAD MUST BE

CONNECTED TO VEE.

Figure 4. HMC674LP3E Pin Configuration

Table 8. HMC674LC3C/HMC674LP3E Pin Function Descriptions

Pin No.

Mnemonic

Description

VTP

Termination Resistor Return Pin for VP Input. See Figure 5 for the interface schematic.

INP

Noninverting Analog Input. See Figure 5 for the interface schematic.

INN

Inverting Analog Input. See Figure 5 for the interface schematic.

VTN

Termination Resistor Return Pin for VN Input. See Figure 5 for the interface schematic.

5, 16

VCCI

Positive Supply Voltage Input Stage. See Figure 6 for the interface schematic.

Latch Enable Input Pin, Inverting Side. See the Theory of Operation section for additional information. See

Figure 6 for the interface schematic.

Latch Enable Input Pin, Noninverting Side. See the Theory of Operation section for additional information. See

Figure 6 for the interface schematic.

NIC

Not Internally Connected. Connect this pin to ground for improved noise.

9, 12

VCCO

Positive Supply Voltage for the Output Stage. See Figure 7 for the interface schematic.

Inverting Output. Q is at logic low if the analog voltage at the noninverting input, INP, is greater than the

analog voltage at the inverting input, INN, provided that the comparator is in track mode. See the Theory of

Operation section for additional information. See Figure 7 for the interface schematic.

Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, INP, is greater than the

analog voltage at the inverting input, INN, provided that the comparator is in track mode. See the Theory of

Operation section for additional information. See Figure 7 for the interface schematic.

VEE

Negative Power Supply, −3 V. See Figure 6 for the interface schematic.

HYS

Hysteresis Control Pin. Leave this pin disconnected for zero hysteresis. Connect this pin to VEE with a resistor to add

the desired amount of hysteresis. See Figure 12 to determine the correct size of the RHYS hysteresis control resistor.

See Figure 8 for the interface schematic.

RTN

Return for ESD Protection.

EPAD

Exposed Pad. The exposed pad must be connected to VEE.

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