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AD9914/PCBZ 数据表(PDF) 7 Page - Analog Devices

部件名 AD9914/PCBZ
功能描述  3.5 GSPS Direct Digital Synthesizer 12-Bit DAC
PDF  45 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9914/PCBZ 数据表(HTML) 7 Page - Analog Devices

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Data Sheet
AD9914
Rev. F | Page 7 of 45
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DATA LATENCY (PIPELINE DELAY)
SYSCLK cycles = fS = system clock frequency
in GHz
Single Tone Mode or Profile Mode
(Matched Latency Disabled)
Frequency
318
SYSCLK cycles
OSK disabled
342
SYSCLK cycles
OSK enabled
Phase
294
SYSCLK cycles
OSK disabled
318
SYSCLK cycles
OSK enabled
Amplitude
102
SYSCLK cycles
OSK enabled
Single Tone Mode or Profile Mode
(Matched Latency Enabled)
Frequency
318
SYSCLK cycles
OSK disabled
342
SYSCLK cycles
OSK enabled
Phase
318
SYSCLK cycles
OSK disabled
342
SYSCLK cycles
OSK enabled
Amplitude
342
SYSCLK cycles
OSK enabled
Modulation Mode with 32-Bit
Parallel Port (Matched Latency
Disabled)
Frequency
318
SYSCLK cycles
OSK disabled
342
SYSCLK cycles
OSK enabled
Phase
294
SYSCLK cycles
OSK disabled
318
SYSCLK cycles
OSK enabled
Amplitude
102
SYSCLK cycles
OSK enabled
Modulation Mode with 32-Bit Parallel
Port (Matched Latency Enabled)
Frequency
318
SYSCLK cycles
OSK disabled
342
SYSCLK cycles
OSK enabled
Phase
318
SYSCLK cycles
OSK disabled
342
SYSCLK cycles
OSK enabled
Amplitude
342
SYSCLK cycles
OSK enabled
Sweep Mode (Match Latency
Disabled)
Frequency
342
SYSCLK cycles
OSK disabled
366
SYSCLK cycles
OSK enabled
Phase
318
SYSCLK cycles
OSK disabled
342
SYSCLK cycles
OSK enabled
Amplitude
126
SYSCLK cycles
OSK enabled
Sweep Mode (Match Latency
Enabled)
Frequency
342
SYSCLK cycles
OSK disabled
366
SYSCLK cycles
OSK enabled
Phase
342
SYSCLK cycles
OSK disabled
366
SYSCLK cycles
OSK enabled
Amplitude
366
SYSCLK cycles
OSK enabled



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