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AD5544BCPZ-R2 数据表(PDF) 9 Page - Analog Devices |
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AD5544BCPZ-R2 数据表(HTML) 9 Page - Analog Devices |
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9 / 24 page ![]() Data Sheet AD5544/AD5554 Rev. H | Page 9 of 24 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AD5544/ AD5554 TOP VIEW (Not to Scale) AGNDA AGNDD IOUTA IOUTD VREFA VREFD RFBA RFBD MSB DGND VSS VDD AGNDF CLK SDO SDI DNC RFBB RFBC VREFB VREFC IOUTB IOUTC AGNDB AGNDC DNC = DO NOT CONNECT. LEAVE THE PIN UNCONNECTED. LDAC CS RS Figure 5. TSSOP Pin Configuration NOTES 1. DNC = DO NOT CONNECT. LEAVE THE PIN UNCONNECTED. 2. CONNECT THE EXPOSED PAD TO AGNDx. 24 VREFD 23 RFBD 22 DGND 21 VSS 20 AGNDF 19 LDAC 18 SDO 17 RFBC 1 2 3 4 5 6 7 8 RFBA MSB RS VDD CS CLK SDI RFBB AD5544 TOP VIEW (Not to Scale) Figure 6. LFCSP Pin Configuration Table 4. Pin Function Descriptions TSSOP Pin No. LFCSP Pin No. Mnemonic Description 1 29 A GNDA DAC A Analog Ground. 2 30 I OUTA DAC A Current Output. 3 32 V REFA DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. This pin can be tied to the V DD pin. 4 1 R FBA DAC A Feedback Resistor Connection. Establish the voltage output for DAC A by connecting this pin to an external amplifier output. 5 2 MSB MSB Bit. Set this pin during a reset pulse (RS) or at system power-on if tied to ground or VDD. 6 3 RS Reset Pin, Active Low Input. Input registers and DAC registers are set to all 0s or half-scale code (0x8000 for the AD5544 and 0x2000 for the AD5554), determined by the voltage on the MSB pin. Register data = 0x0000 when MSB = 0. 7 4 V DD Positive Power Supply Input. Specified range of operation: 5 V ± 10%. 8 5 CS Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register data to the input register when CS/LDAC returns high. Does not affect LDAC operation. 9 6 CLK Clock Input. Positive edge clocks data into the shift register. 10 7 SDI Serial Data Input. Input data loads directly into the shift register. 11 8 R FBB DAC B Feedback Resistor Connection. Establish the voltage output for DAC B by connecting this pin to an external amplifier output. 12 10 V REFB DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. This pin can be tied to the V DD pin. 13 11 I OUTB DAC B Current Output. 14 12 A GNDB DAC B Analog Ground. 15 13 A GNDC DAC C Analog Ground. 16 14 I OUTC DAC C Current Output. 17 15 V REFC DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. This pin can be tied to the V DD pin. 18 17 R FBC DAC C Feedback Resistor Connection. Establish the voltage output for DAC C by connecting this pin to an external amplifier output. 19 9, 16, 25, 26, 31 DNC Do Not Connect. Leave these pins unconnected. 20 18 SDO Serial Data Output. Input data loads directly into the shift register. Data appears at SDO at 19 clock pulses for the AD5544 and 17 clock pulses for the AD5554 after input at the SDI pin. 21 19 LDAC Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC registers. Asynchronous active low input. See Table 8 and Table 9 for operation. |
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