AD5544/AD5554

Data Sheet

Rev. H | Page 16 of 24

SERIAL DATA INTERFACE

The AD5544/AD5554 use a 3-wire (CS, SDI, CLK), SPI-compatible

serial data interface. Serial data of the AD5544/AD5554 is clocked

into the serial input register in an 18-bit and 16-bit data-word

format, respectively. The MSB bits are loaded first. Table 5 defines

the 18 data-word bits for the AD5544, and Table 6 defines the

16 data-word bits for the AD5554. Data is placed on the SDI pin

and clocked into the register on the positive clock edge of CLK,

subject to the data setup and data hold time requirements specified

in the interface timing specifications (see Table 1 and Table 2).

Data can be clocked in only while the CS chip select pin is active

low. For the AD5544, only the last 18 bits clocked into the serial

register are interrogated when the CS pin returns to the logic high

state; extra data bits are ignored. For the AD5554, only the last

16 bits clocked into the serial register are interrogated when the

CS pin returns to the logic high state. Because most microcontrol-

lers output serial data in 8-bit bytes, three right justified data bytes

can be written to the AD5544. Keeping the CS line low between

the first, second, and third byte transfers results in a successful

serial register update.

Similarly, two right justified data bytes can be written to the

AD5554. Keeping the CS line low between the first and second

byte transfer results in a successful serial register update.

When the data is properly aligned in the shift register, the posi-

tive edge of the CS initiates the transfer of new data to the target

DAC register, determined by the decoding of Address Bit A1

and Address Bit A0. For the AD5544, Table 5, Table 7, Table 8,

and Figure 3 define the characteristics of the software serial

interface.

For the AD5554, Table 6, Table 7, Table 9, and Figure 4 define

the characteristics of the software serial interface. Figure 23 and

Figure 24 show the equivalent logic interface for the key digital

control pins for the AD5544. The AD5554 has a similar configura-

tion, except that it has 14 data bits. Two additional pins, RS and

MSB, provide hardware control over the preset function and

DAC register loading. If these functions are not needed, the RS

pin can be tied to logic high. The asynchronous input RS pin

forces all input and the DAC registers to either the zero-code

state (MSB = 0) or the half-scale state (MSB = 1).

MSB

LSB

B17

B16

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

A1

A0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

internally generated load strobe transfers the serial register data contents (Bit D15 to Bit D0) to the decoded DAC input register address determined by Bit A1 and Bit A0.

Any extra bits clocked into the AD5544 shift register are ignored; only the last 18 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be

tied logic low to disable the DAC registers.

MSB

LSB

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

A1

A0

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

internally generated load strobe transfers the serial register data contents (Bit D13 to Bit D0) to the decoded DAC input register address determined by Bit A1 and Bit A0.

Any extra bits clocked into the AD5554 shift register are ignored; only the last 16 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be

tied logic low to disable the DAC registers.

Table 7. Address Decode

A1

A0

DAC Decoded

0

0

DAC A

0

1

DAC B

1

0

DAC C

1

1

DAC D