32F030F4P6 datasheet(68/93 Pages) STMICROELECTRONICS

68 / 93 page

Electrical characteristics

STM32F030x4/x6/x8/xC

68/93

DS9773 Rev 4

Equation 1: RAIN max formula

The formula above (Equation 1) is used to determine the maximum external impedance

allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

tCAL(2)(3)

Calibration time

fADC = 14 MHz

5.9

µs

-83

1/fADC

WLATENCY(2)(4)

ADC_DR register write

latency

ADC clock = HSI14

1.5 ADC

cycles + 2

fPCLK cycles

1.5 ADC

cycles + 3

fPCLK cycles

ADC clock = PCLK/2

4.5

fPCLK

cycle

ADC clock = PCLK/4

8.5

fPCLK

cycle

tlatr(2)

Trigger conversion

latency

fADC = fPCLK/2 =

14 MHz

0.196

µs

fADC = fPCLK/2

5.5

1/fPCLK

fADC = fPCLK/4 =

12 MHz

0.219

µs

fADC = fPCLK/4

10.5

1/fPCLK

fADC = fHSI14 = 14 MHz

0.188

0.259

µs

JitterADC

ADC jitter on trigger

conversion

fADC = fHSI14

-1-

1/fHSI14

tS(2)

Sampling time

fADC = 14 MHz

0.107

17.1

µs

1.5

239.5

1/fADC

tSTAB(2)

Stabilization time

1/fADC

tCONV(2)

Total conversion time

(including sampling time)

fADC = 14 MHz,

12-bit resolution

µs

12-bit resolution

14 to 252 (tS for sampling +12.5 for

successive approximation)

1/fADC

1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on IDDA and 60 µA

on IDD should be taken into account.

2. Guaranteed by design, not tested in production.

3. Specified value includes only ADC timing. It does not include the latency of the register access.

4. This parameter specify latency for transfer of the conversion result to the ADC_DR register. EOC flag is set at this time.

Table 50. ADC characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

RAIN

fADC CADC

()

---------------------------------------------------------------- RADC

–

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