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PIFE32251B-R47MS 数据表(PDF) 45 Page - Texas Instruments

部件名 PIFE32251B-R47MS
功能描述  PMIC for Intel Apollo Lake Platform
PDF  96 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

PIFE32251B-R47MS 数据表(HTML) 45 Page - Texas Instruments

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S0
SLP_S0B
VTT
BUCK1 (VNN)
PCH_PWROK
S0iX
S0
BUCK2 (VCCGI)
BUCK3 (VCCRAM)
SLP_S3B
SLP_S4B
3.3 V
1.8 V
1.05 V
0 V
0 V
Host sets VR to 0 V through I
2C
Host sets VR to 0 V through I
2C
0 V
˜ 100 µs
VID
VID
VID
SET VID by Host
˜ 5 ms
45
TPS65094
www.ti.com
SWCS133C – SEPTEMBER 2015 – REVISED FEBRUARY 2019
Submit Documentation Feedback
Product Folder Links: TPS65094
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
6.3.5.3
Connected Standby Entry and Exit
Figure 6-9. Connected Standby Entry and Exit Sequence
S0 to S0iX (Connected Standby) entry and exit occurs when SLP_S0B is pulled low and high,
respectively. In Connected Standby state, VTT LDO is turned off, but all PGOODs remain asserted.
BUCK1–BUCK3 are not disabled, but instead stop switching while BUCK4–BUCK6 remain in regulation.
SWB1_2 also stays enabled. On entry, BUCK2 and BUCK3 decay to 0 V with their VID registers retaining
the last programmed values to which the BUCKs ramp back up on exit. The host can write to
BUCK2CTRL and BUCK3CTRL registers regardless of the state of the SLP_S0B pin while SLP_S3B and
SLP_S4B are high, which means that BUCK2 and BUCK3 can be changed to ramp to a different voltage
upon exiting S0iX than they had when entering S0iX state. BUCK1 ramps back up to the default value
(1.05 V).
Table 6-11 summarizes status of each VR in Connected Standby state.
Table 6-11. Summary of Rails on Connected Standby Entry and Exit
VR
S0
→ S0IX
S0IX
→ S0
BUCK1 (VNN)
0 V
1.05 V
BUCK2 (VCCGI)
0 V
0 V
BUCK3 (VCCRAM)
0 V
1.05 V
BUCK4 (V1P8A)
VID value
VID value
BUCK5 (V1P24A)
VID value
VID value
BUCK6 (VDDQ)
OTP dependent
OTP dependent
VTT LDO (VTT)
OFF
VDDQ / 2
SWB1_2
ON
ON



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