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PIFE32251B-R47MS 数据表(PDF) 54 Page - Texas Instruments |
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PIFE32251B-R47MS 数据表(HTML) 54 Page - Texas Instruments |
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54 / 96 page  54 TPS65094 SWCS133C – SEPTEMBER 2015 – REVISED FEBRUARY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: TPS65094 Detailed Description Copyright © 2015–2019, Texas Instruments Incorporated 6.6.3 IRQ: PMIC Interrupt Register (offset = 02h) [reset = 0000 0000] Figure 6-21. IRQ Register (offset = 02h) [reset = 0000 0000] Bit 7 6 5 4 3 2 1 0 Bit Name VENDOR_ IRQ RESERVED RESERVED RESERVED ONOFFSRC RESERVED RESERVED DIETEMP TPS65094x 0 0 0 0 0 0 0 0 Access R/W R R R R/W R R R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-14. IRQ Register Field Descriptions Bit Field Type Reset Description 7 VENDOR_IRQ R/W 0 Vendor-specific interrupt, indicating fault event occurrence. Asserted when either one of following conditions occurs: A. Deassertion of Power Good of any VR B. Overcurrent detection from BUCK1, BUCK2, BUCK6, or VTT LDO C. Die temperature crosses over the hot temperature threshold (THOT) D. Die temperature crosses over the critical temperature threshold (TCRIT) 0: Not asserted 1: Asserted. Host to write 1 to clear. 3 ONOFFSRC R/W 0 Asserted when PMIC shuts down. 0: Not asserted. 1: Asserted. Host to write 1 to clear. 0 DIETEMP R/W 0 Die Temp interrupt. Asserted when PMIC die temperature crosses above the hot temperature threshold (THOT). 0: Not asserted. 1: Asserted. Host to write 1 to clear. 6.6.4 IRQ_MASK: PMIC Interrupt Mask Register (offset = 03h) [reset = 1111 1111] Figure 6-22. IRQ_MASK Register (offset = 03h) [reset = 1111 1111] Bit 7 6 5 4 3 2 1 0 Bit Name MVENDOR_IRQ RESERVED RESERVED RESERVED MONOFFSRC RESERVED RESERVED MDIETEMP TPS65094x 1 1 1 1 1 1 1 1 Access R/W R R R R/W R R R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-15. IRQ_MASK Register Field Descriptions Bit Field Type Reset Description 7 MVENDOR_IRQ R/W 1 Vendor-specific fault interrupt mask. 0: Not masked 1: Masked 3 MONOFFSRC R/W 1 PMIC shutdown event interrupt mask 0: Not masked 1: Masked 0 MDIETEMP R/W 1 Die temp interrupt mask. 0: Not masked 1: Masked |
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