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NUC505-YO2T 数据表(PDF) 121 Page - Nuvoton Technology Corporation |
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NUC505-YO2T 数据表(HTML) 121 Page - Nuvoton Technology Corporation |
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121 / 130 page  NUC505 July. 26, 2018 Page 121 of 130 Rev.1.08 7.4.9 I 2S Dynamic Characteristics Symbol Parameter Min. Max. Unit Test Conditions th(WS) I2S clock high time 42 - ns Master fPCLK = 12.288 MHz, data: 24 bits, audio frequency = 48 kHz tsu(WS) I2S clock low time 37 - th(WS) LRCLK valid time 7 - Master mode DuCy(SCK) LRCLK hold time 1 - Master mode tsu(SD_MR) LRCLK setup time 34 - Slave mode tsu(SD_SR) LRCLK hold time 0 - Slave mode th(SD_MR) I2S slave input clock duty cycle 25 75 % Slave mode th(SD_SR) Data input setup time 0 - ns Master receiver tv(SD_ST) 0 - Slave receiver th(SD_ST) Data input hold time 0 - Master receiver tv(SD_MT) 0 - Slave receiver th(SD_MT) Data output valid time - 32 Slave transmitter (after enable edge) th(WS) Data output hold time 16 - Slave transmitter (after enable edge) tsu(WS) Data output valid time - 5 Master transmitter (after enable edge) th(WS) Data output hold time 0 - Master transmitter (after enable edge) |
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