REV. 0

ADE7756

–31–

Interrupt Status Register (04H) / Reset Interrupt Status Register (05H)

The Status register is used by the MCU to determine the source of an interrupt request (

IRQ). When an interrupt event occurs in the

ADE7756, the corresponding flag in the Interrupt Status register is set logic high. If the enable bit for this flag is Logic 1 in the Inter-

rupt Enable register, the

IRQ logic output goes active low. When the MCU services the interrupt it must first carry out a read from

the Interrupt Status register to determine the source of the interrupt.

Table VII. Interrupt Status Register, Reset Interrupt Status Register and Interrupt Enable Register

Bit

Interrupt

Location

Flag

Description

0

AEHF

Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the Active Energy register.

1

SAG

Indicates that an interrupt was caused by a SAG on the line voltage or no zero crossings were detected.

In calibration mode this flag is also used to indicate the end of an integration over an integer number of

half line cycles—see Energy Calibration section.

3

WSMP

Indicates that new data is present in the Waveform register.

4

ZX

This status bit reflects the status of the ZX logic output—see Zero Crossing Detection section.

5

TEMP

Indicates that a temperature conversion result is available in the Temperature register.

7

AEOF

Indicates that the Active Energy register has overflowed.

INTERRUPT STATUS REGISTER*

ADDR: 04H / RESET: 05H

AEOF

(ACTIVE ENERGY REGISTER OVERFLOW)

RESERVED = 0

TEMP

ZX

*REGISTER CONTENTS SHOW POWER-ON DEFAULTS

0

000

00

00

7654

32

10

AEHF

(ACTIVE ENERGY REGISTER HALF FULL)

SAG

(LINE VOLTAGE SAG DETECT)

RESERVED = 0

WSMP

(WAVEFORM SAMPLING)

Figure 42. Interrupt Status Register

INTERRUPT ENABLE REGISTER*

ADDR: 10H

AEOF

(ACTIVE ENERGY REGISTER OVERFLOW)

RESERVED = 0

TEMP

ZX

*REGISTER CONTENTS SHOW POWER-ON DEFAULTS

0

000

00

00

7654

32

10

AEHF

(ACTIVE ENERGY REGISTER HALF FULL)

SAG

(LINE VOLTAGE SAG DETECT)

RESERVED = 0

WSMP

(WAVEFORM SAMPLING)

Figure 43. Interrupt Enable Register