ADE7756ARS datasheet(18/32 Pages) AD

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REV. 0

ADE7756

–18–

CHANNEL 1 ADC

Figure 18 shows the ADC and signal processing chain for Chan-

nel 1. In waveform sampling mode the ADC outputs a signed

two’s complement 20-bit data word at a maximum of 27.9 kSPS

(CLKIN/128). The output of the ADC can be scaled by

±50% to

perform an overall power calibration or to calibrate the ADC out-

put. While the ADC outputs a 20-bit two’s complement value, the

maximum full-scale positive value from the ADC is limited to

40000h (+262,144 decimal). The maximum full-scale negative

value is limited to C0000h (–262,144 Decimal). If the analog

inputs are overranged, the ADC output code will clamp at these

values. With the specified full scale analog input signal of 1 V (or

0.5 V or 0.25 V—see Analog Inputs section) the ADC will produce

an output code which is approximately 63% of its full-scale value.

This is illustrated in Figure 18. The diagram in Figure 15 shows

a full-scale voltage signal being applied to the differential inputs

V1P and V1N. The ADC output swings between D7AE1h

(–165,151) and 2851Fh (+165,151). This is approximately 63%

of the full-scale value 40000h (262,144). Overranging the analog

inputs with more than 1 V differential (0.5 or 0.25, depending

on Channel 1 full-scale selection) will cause the ADC output to

increase towards its full-scale value. However for specified opera-

tion the differential signal on the analog inputs should not exceed

the recommended value of 1.0 V.

Channel 1 ADC Gain Adjust

The ADC gain in Channel 1 can be adjusted by using the multi-

plier and Active Power Gain register (APGAIN[11:0]). The

gain of the ADC is adjusted by writing a two’s complement

12-bit word to the Active Power Gain register. Following is

801Hex – 7FFHex

x1, x2, x4,

x8, x16

REFERENCE

2.42V, 1.21V, 0.6V

APGAIN[11:0]

00000h

40000h

C0000h

2851Fh

D7AE1h

+FS

–FS

+63% FS

–63% FS

00000h

2851Fh

+63% FS

–63% FS

D7AE1h

+94.5% FS

+31.5% FS

–31.5% FS

–94.5% FS

3C7AEh

1428Fh

EBD71h

C3852h

000h 7FFh 801h

ANALOG INPUT

RANGE

ADC OUTPUT

WORD RANGE

CHANNEL 1 (ACTIVE POWER)

CALIBRATION RANGE

MULTIPLIER

WAVEFORM

WAVEFORM[23:0]

DIGITAL

LPF

1V, 0.5V, 0.25V, 125mV,

62.5mV, 31.3mV, 15.6mV

GAIN[4:3]

MULTIPLIER

HPF

V1P

V1N

SINC3

ADC

GAIN[2:0]

PGA1

APGAIN[11:0]

Figure 18. ADC and Signal Processing in Channel 1

the expression that shows how the gain adjustment is related to

the contents of the Active Power Gain register.

Code

ADC

APGAIN

=× +





















For example when 7FFh is written to the Active Power Gain

mal, 2047/2

12 = 0.5. Similarly, 801h = –2047 decimal (signed

two’s complement) and ADC output is scaled by –50%. These

two examples are graphically illustrated in Figure 18.

Channel 1 Sampling

The waveform samples may also be routed to the Waveform

(MCU). In waveform sampling mode the WSMP bit (Bit 3) in

the Interrupt Enable register must also be set to Logic 1. The

Active Power and Energy calculation will remain uninterrupted

during waveform sampling.

When in waveform sample mode, one of four output sample rates

may be chosen by using Bits 11 and 12 of the Mode register

(WAVSEL1, 0). The output sample rate may be 27.9 kSPS,

14 kSPS, 7 kSPS or 3.5 kSPS—see Mode Register section. The

interrupt request output

IRQ signals a new sample availability

by going active low. The timing is shown in Figure 19. The

20-bit waveform samples are transferred from the ADE7756 one

byte (8 bits) at a time, with the most significant byte shifted out

first. The 20-bit data word is right-justified and sign extended

to 24 bits (three bytes)—see Serial Interface section.

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