REV. 0

ADE7756

–29–

Table IV. Register List (continued)

No. of

Address

Name

R/W

Bits

Default

Description

10H

IRQEN

R/W

8

0h

Interrupt Enable Register. ADE7756 interrupts may be deactivated at

any time by setting the corresponding bit in this 8-bit Enable register

Logic 0. The Status register will continue to register an interrupt event

even if disabled. However, the

IRQ output will not be activated

—see Interrupts section.

11H

SAGLVL

R/W

8

0h

Sag Voltage Level. An 8-bit write to this register determines at what

peak signal level on Channel 2 the SAG pin will become active. The

signal must remain low for the number of cycles specified in the SAGCYC

register before the SAG pin is activated—see Line Voltage Sag Detec-

tion section.

12H

TEMP

R

8

0h

Temperature Register. This is an 8-bit register which contains the result

of the latest temperature conversion. A full description of this register’s

contents can be found in the Temperature Measurement section of this

data sheet.

REGISTER DESCRIPTIONS

All ADE7756 functionality is accessed via the on-chip registers. Each register is accessed by first writing to the communications

register and then transferring the register data. A full description of the serial interface protocol is given in the Serial Interface section

of this data sheet.

Communications Register

The Communications register is an 8-bit, write-only register that controls the serial data transfer between the ADE7756 and the host

processor. All data transfer operations must begin with a write to the communications register. The data written to the communica-

tions register determines whether the next operation is a read or a write and which register is being accessed. Table V outlines the bit

designations for the Communications register.

Table V. Communications Register

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

W/

R

0

0

A4

A3

A2

A1

A0

Bit

Bit

Location

Mnemonic

Description

0 to 4

A0 to A4

The five LSBs of the Communications register specify the register for the data transfer opera-

tion. Table IV lists the address of each ADE7756 on-chip register.

5 to 6

RESERVED

These bits are unused and should be set to zero.

7W/

R

When this bit is a Logic 1, the data transfer operation immediately following the write to the

Communications register will be interpreted as a write to the ADE7756. When this bit is a

Logic 0, the data transfer operation immediately following the write to the Communications

register will be interpreted as a read operation.