ADE7756ARS datasheet(28/32 Pages) AD

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ADE7756

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Table IV. Register List

No. of

Address

Name

R/W

Bits

Default

Description

00h

Not Used

No Operation.

01h

WAVEFORM

The Waveform register is a 24 bit read-only register. This register

contains the sampled waveform data from either Channel 1, Channel 2

or the Active Power signal. The data source is selected by data bits 14

and 13 in the Mode Register—see Channel 1 and 2 Sampling sections.

02h

AENERGY

The Active Energy Register. Active Power is accumulated (Integrated)

over time in this 40-bit, read-only register. The energy register can hold a

minimum of 6 seconds of Active Energy information with full-scale

analog inputs before it overflows—see Energy Calculation section.

03h

RSTENERGY

Same as the Active Energy register except that the register is reset to

zero following a read operation

04h

STATUS

The Interrupt Status Register. This is an 8-bit read-only register. The

Status Register contains information regarding the source of ADE7756

interrupts—see Interrupts section.

05h

RSTSTATUS

Same as the Interrupt Status register except that the register contents

are reset to zero (all flags cleared) after a read operation.

06h

MODE

R/W

000Ch

The Mode Register. This is a 16-bit register through which most of the

ADE7756 functionality is accessed. Signal sample rates, filter enabling

and calibration modes are selected by writing to this register. The contents

may be read at any time—see Mode Register section.

07h

CFDIV

R/W

3Fh

The Frequency Divider Register. This is a 12-bit read/write register.

The output frequency on the CF pin is adjusted by writing to this

08h

CH1OS

R/W

Channel 1 Offset Adjust. Writing to this 6-bit register allows any off-

sets on Channel 1 to be removed—see Analog Inputs section.

09h

CH2OS

R/W

Channel 2 Offset Adjust. Writing to this 6-bit register allows any off-

sets on Channel 2 to be removed—see Analog Inputs section.

0Ah

GAIN

R/W

PGA Gain Adjust. This 8-bit register is used to adjust the gain selec-

tion for the PGA in Channel 1 and Channel 2—Analog Inputs section.

0Bh

APGAIN

R/W

Active Power Gain Adjust. This is a 12-bit register. The Active Power

calculation can be calibrated by writing to this register. The calibration

range is

± 50% of the nominal full scale active power. The resolution

of the gain adjust is 0.0244%/LSB—see Channel 1 ADC Gain

Adjust section.

0Ch

PHCAL

R/W

Phase Calibration Register. The phase relationship between Channel 1

and Channel 2 can be adjusted by writing to this 6-bit register. The

adjustment range is approximately

±3.1° at 60 Hz in 0.097° steps—see

Phase Compensation section.

0Dh

APOS

R/W

Active Power Offset Correction. This 12-bit register allows small off-

sets in the Active Power Calculation to be removed—see Active Power

Calculation section.

0Eh

ZXTOUT

R/W

FFFFh

Zero-Cross Time Out. If no zero crossings are detected on Channel 2

within a time period specified by this 12-bit register, the interrupt

request line (

IRQ) will be activated. The maximum time-out period is

0.15 second—see Zero Crossing Detection section.

0Fh

SAGCYC

R/W

FFh

Sag Line Cycle Register. This 8-bit register specifies the number of

consecutive half line cycles the signal on Channel 2 must be below

SAGLVL before the SAG output is activated—see Voltage Sag Detec-

tion section. It is also used during calibration mode to set the number

of line cycles Active power is accumulated for Energy calibration—see

Energy Calibration section.

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