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GD25Q80CSIG 数据表(PDF) 32 Page - GigaDevice Semiconductor (Beijing) Inc.

部件名 GD25Q80CSIG
功能描述  3.3V Uniform Sector Dual and Quad Serial Flash
PDF  67 Pages
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制造商  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
网页  http://www.gigadevice.com/
标志 GIGADEVICE - GigaDevice Semiconductor (Beijing) Inc.

GD25Q80CSIG 数据表(HTML) 32 Page - GigaDevice Semiconductor (Beijing) Inc.

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3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q80C
32
Figure 26. Read Identification ID Sequence Diagram
7.24.
High Performance Mode (HPM) (A3H)
The High Performance Mode (HPM) command must be executed prior to Dual or Quad I/O commands when
operating at high frequencies (see fR and fC1 in AC Electrical Characteristics). This command allows pre-charging of
internal charge pumps so the voltages required for accessing the flash memory array are readily available. The
command sequence: CS# goes lowSending A3H command Sending 3-dummy ByteCS# goes high. See Figure
27. After the HPM command is executed, HPF bit of status register will be set to 1, the device will maintain a slightly
higher standby current (Icc9) than standard SPI operation. The Release from Power-Down or HPM command (ABH) can
be used to return to standard SPI standby current (Icc1). In addition, Power-Down command (B9H) will also release
the device from HPM mode back to standard SPI standby state.
Figure 27. High Performance Mode Sequence Diagram
0
1
2
3
4
5
6
7
CS#
SCLK
SI
SO
8
9 10
MSB
18 19 20 21
17
6
5
4
3
2
1
0
22 23
16
26 27 28 29
25
30 31
24
7
Capacity
JDID7-JDID0
CS#
SCLK
SI
SO
MSB
Memory Type
JDID15-JDID8
6
5
4
3
2
1
0
7
11 12 13 14 15
9FH
6
5
4
3
2
1
0
7
Manufacturer ID
MSB
Command
Command
0
1
2 3
4
5
6
7
A3H
CS#
SCLK
SI
8
9
29 30 31
MSB
2
1
0
3 Dummy Bytes
23 22
SO
High Performance Mode
HPM
t



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