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GD25Q80CSIG 数据表(PDF) 9 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25Q80CSIG 数据表(HTML) 9 Page - GigaDevice Semiconductor (Beijing) Inc. |
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9 / 67 page ![]() 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q80C 9 5. DATA PROTECTION The GD25Q80C provide the following data protection methods: ◆ Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will return to reset by the following situation: -Power-Up -Write Disable (WRDI) -Write Status Register (WRSR) -Page Program (PP) -Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE) ◆ Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits define the section of the memory array that can be read but not change. ◆ Hardware Protection Mode: WP# goes low to protect the writable bit of Status Register. ◆ Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down Mode command and reset command (66H+99H). Table1.0 GD25Q80C Protected area size (CMP=0) Status Register Content Memory Content BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion X X 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 15 0F0000H-0FFFFFH 64KB Upper 1/16 0 0 0 1 0 14to 15 0E0000H-0FFFFFH 128KB Upper 1/8 0 0 0 1 1 12to 15 0C0000H-0FFFFFH 256KB Upper 1/4 0 0 1 0 0 8 to 15 080000H-0FFFFFH 512KB Upper 1/2 0 1 0 0 1 0 000000H-00FFFFH 64KB Lower 1/16 0 1 0 1 0 0 to 1 000000H-01FFFFH 128KB Lower 1/8 0 1 0 1 1 0 to 3 000000H-03FFFFH 256KB Lower 1/4 0 1 1 0 0 0 to 7 000000H-07FFFFH 512KB Lower 1/2 0 X 1 0 1 0 to 15 000000H-0FFFFFH 1MB ALL X X 1 1 X 0 to 15 000000H-0FFFFFH 1MB ALL 1 0 0 0 1 15 0FF000H-0FFFFFH 4KB Top Block 1 0 0 1 0 15 0FE000H-0FFFFFH 8KB Top Block 1 0 0 1 1 15 0FC000H-0FFFFFH 16KB Top Block 1 0 1 0 X 15 0F8000H-0FFFFFH 32KB Top Block 1 1 0 0 1 0 000000H-000FFFH 4KB Bottom Block 1 1 0 1 0 0 000000H-001FFFH 8KB Bottom Block 1 1 0 1 1 0 000000H-003FFFH 16KB Bottom Block 1 1 1 0 X 0 000000H-007FFFH 32KB Bottom Block |
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