GD25Q80CSFG datasheet(17/67 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q80C

Figure4. Read Status Register Sequence Diagram

7.4. Write Status Register (WRSR) (01H)

The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be

accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN)

command has been decoded and executed, the device sets the Write Enable Latch (WEL).

The Write Status Register (WRSR) command has no effect on S15, S13, S1 and S0 of the Status Register. CS# must

be driven high after the eighth or sixteen bit of the data Byte has been latched in. If not, the Write Status Register (WRSR)

command is not executed. If CS# is driven high after eighth bit of the data Byte, the CMP and QE bit will be cleared to 0.

As soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write

Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP)

bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.

When the cycle is completed, the Write Enable Latch (WEL) is reset.

The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3,

BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table1. The Write Status

the Write Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the device to

be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is not executed once the Hardware

Protected Mode is entered.

Figure5. Write Status Register Sequence Diagram

7.5. Write Enable for Volatile Status Register (50H)

The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the

system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or

affecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command

must be issued prior to a Write Status Register command and any other commands cannot be inserted between them.

Otherwise, Write Enable for Volatile Status Register will be cleared. The Write Enable for Volatile Status Register command

will not set the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status

Command

05H or 35H

CS#

SCLK

High-Z

9 10 11 12 13 14 15

MSB

S7~S0 or S15~S8 out

MSB

Command

01H

CS#

SCLK

High-Z

9 10 11 12 13 14 15

MSB

Status Register in

16 17 18 19 20 21 22 23

15 14 13 12 11 10 9

GD25Q80CSFG 数据表(PDF) 17 Page - GigaDevice Semiconductor (Beijing) Inc.

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