AW9233CSR datasheet(12/48 Pages) AWINIC

12 / 48 page

AW9233

June 2018 V1.2

www.awinic.com.cn

R/W

Figure 5

Device Address Configuration

9.3.2

Data Validation

When SCL is high level, SDA level must be constant. SDA can be changed only when SCL is low level.

SCL

SDA

Data Line

Stable

Data Valid

Change

of Data

Allowed

Figure 6

Data Validation Diagram

9.3.3

ACK(Acknowledgement)

ACK means the successful transfer of I2C bus data. After master sends 8bits data, SDA must be released;

SDA is pulled to GND by slave device when slave acknowledges.

When master reads, AW9233 sends 8bit data, releases the SDA and waits for ACK from master. If ACK is

send and I2C stop is not send by master, AW9233 sends the next data. If ACK is not send by master, AW9233

stops to send data and waits for I2C stop.

Data Output

by Transmiter

Data Output

by Receiver

SCL From

Master

START

condition

Not Acknowledge（NACK）

Acknowledge（ACK）

Clock Pulse for

Acknowledgement

Figure 7

I2C ACK Timing

9.3.4

I2C Start/Stop

I2C start: SDA changes form high level to low level when SCL is high level.

I2C stop: SDA changes form low level to high level when SCL is high level.

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