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AW9233CSR 数据表(PDF) 32 Page - Shanghai awinic technology co.,ltd

部件名 AW9233CSR
功能描述  3-Key Capacitive Touch Controller Integrated with 3-LED Driver
PDF  48 Pages
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制造商  AWINIC [Shanghai awinic technology co.,ltd]
网页  http://www.awinic.com.cn/index.php
标志 AWINIC - Shanghai awinic technology co.,ltd

AW9233CSR 数据表(HTML) 32 Page - Shanghai awinic technology co.,ltd

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AW9233
June 2018 V1.2
www.awinic.com.cn
32
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
10.3.8
SCFG1, Scan Configuration Register
Address: 0x11, R/W, default: 0x0004
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
SCNMD
0
0
SCNUM
Bit
Symbol
Description
4:0
SCNUM
Scan cycle number, default value is 4. The bigger scan cycle number, the longer
scan time, and the higher the detection sensitivity.
SCNUM=0,
256
SCNUM!=0,
SCNUM*512
7
SCNMD
Scan mode
0: scan all keys, the cycle time is constant
1: scan the selected keys
15~8
-
Reserved, must be 0
10.3.9
SCFG2, Scan Configuration Register
Address: 0x12, R/W, default: 0x0107
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
SEED
RFFLTEN
0
SENS
Bit
Symbol
Description
3:0
SENS
Sensitivity configuration, there are 16 level available. The less the value of SENS,
the higher the sensitivity. 0000 is the highest sensitivity, 1111 is the lowest
sensitivity, the default value is 0111.
5:4
-
Reserved, must be 0
7:6
RFFLTEN
RF filter enable, when enable RF filter, SCFG1.SCNUM should be bigger than 4.
00: RF filter off (default)
01: RF filter mode 1 enable
10: RF filter mode2 enable
11: RF filter off
10:8
SEED
ADC output data length selection
000:
ADC/16
001:
ADC/8 (default)
010:
ADC/4
011:
ADC/2
100:
ADC/1
10.3.10
OFSR1, Key Capacitance Offset Register
Address: 0x14, R/W, default: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
OFSEN2
OFFSET2
0
0
0
OFSEN1
OFFSET1
Bit
Symbol
Description
3:0
OFFSET1
S1 capacitance offset value
4
OFSEN1
S1 capacitance offset enable
7:5
-
Reserved, must be 0
11:8
OFFSET2
S2 capacitance offset value
12
OFSEN2
S2 capacitance offset enable
15:13
-
Reserved, must be 0
10.3.11
OFSR2, Key Capacitance Offset Register
Address: 0x15, R/W, default: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
OFSEN3
OFFSET3
Bit
Symbol
Description
3:0
OFFSET3
S3 capacitance offset value
4
OFSEN3
S3 capacitance offset enable
7:5
-
Reserved, must be 0
15:8
-
Reserved, must be 0



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