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GD5F1GQ4REFJS 数据表(PDF) 14 Page - GigaDevice Semiconductor (Beijing) Inc.

部件名 GD5F1GQ4REFJS
功能描述  SPI(x1/x2/x4) NAND Flash
PDF  60 Pages
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制造商  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
网页  http://www.gigadevice.com/
标志 GIGADEVICE - GigaDevice Semiconductor (Beijing) Inc.

GD5F1GQ4REFJS 数据表(HTML) 14 Page - GigaDevice Semiconductor (Beijing) Inc.

Back Button GD5F1GQ4REFJS Datasheet HTML 10Page - GigaDevice Semiconductor (Beijing) Inc. GD5F1GQ4REFJS Datasheet HTML 11Page - GigaDevice Semiconductor (Beijing) Inc. GD5F1GQ4REFJS Datasheet HTML 12Page - GigaDevice Semiconductor (Beijing) Inc. GD5F1GQ4REFJS Datasheet HTML 13Page - GigaDevice Semiconductor (Beijing) Inc. GD5F1GQ4REFJS Datasheet HTML 14Page - GigaDevice Semiconductor (Beijing) Inc. GD5F1GQ4REFJS Datasheet HTML 15Page - GigaDevice Semiconductor (Beijing) Inc. GD5F1GQ4REFJS Datasheet HTML 16Page - GigaDevice Semiconductor (Beijing) Inc. GD5F1GQ4REFJS Datasheet HTML 17Page - GigaDevice Semiconductor (Beijing) Inc. GD5F1GQ4REFJS Datasheet HTML 18Page - GigaDevice Semiconductor (Beijing) Inc. Next Button
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SPI(x1/x2/x4) NAND Flash
1G
14
6
WRITE OPERATIONS
6.1 Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit
must be set prior to following operations that change the contents of the memory array:
• Page program
• OTP program/OTP protection
• Block erase
The WEL bit can be cleared after a reset command.
Figure6-1. Write Enable Sequence Diagram
Command
0
1
2
3
4
5
6
7
06H
CS#
SCLK
SI
SO
High-Z
6.2 Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The WEL bit is also reset by following
condition:
• Page program
• OTP program/OTP protection
• Block erase
Figure6-2. Write Disable Sequence Diagram
Command
0
1
2
3
4
5
6
7
04H
CS#
SCLK
SI
SO
High-Z



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