MT7697DN datasheet(20/84 Pages) ETC2

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MT7697D

Internet-of-Things Wireless Connectivity

Page 20 of 84

This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

2.3.2

Reset

MT7697D has three global resets: XRESETN, CM4_RESETN, and N9_RESETN. The figure below shows

the module that the reset signals are applied to.

CM4_RESETN Reset Tree

CM4 MCU and all modules on CM4 bus other than XRESETN reset

tree

N9_RESETN Reset Tree

N9 MCU and all modules on N9 bus other than XRESETN reset

tree

Chip Cold Reset Event

N9 Host Reset Event

Chip Cold Reset Event

CM4 Host Reset Event

XRESETN Reset Tree

(1)CM4 WDT and GPT module

(2)CM4 WIC module

(3)N9 WDT and GPT module

(4)N9 interrupt module

(5)AON module (top MISC logic always on during sleep)

Chip Cold Reset Event

Figure 2-5. Reset Structure

2.4

Application Processor Subsystem

The MCU subsystem consists of a 32-bit MCU, the AHB/APB bus matrix, internal RAM/ROM with

ROM patch function, the flash controller, and the system peripherals including Direct Memory Access

(DMA) engine and the General Purpose Timer (GPT).

2.4.1

CPU

MT7697D features an ARM Cortex-M4 processor, which is the most energy efficient ARM processor

available. It supports the clock rates from 1MHz up to 192MHz.

The MCU executes the Thump-2 instruction set for optimal performance and code size, including

hardware division, single cycle multiplication, and bit-field manipulation.

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