MT7697DN datasheet(32/84 Pages) ETC2

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MT7697D

Internet-of-Things Wireless Connectivity

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This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

2.4.10.3 Reset Scenarios

The definitions of the cold reset and the warm reset are shown below:



Cold Reset: Power on reset and both RAM or peripheral devices will be initialized by

firmware.



Warm Reset: CPU is reset but RAM content is still retained (without firmware re-

download). It’s triggered by

o Software reset: Software set WDT reset control register to reset CPU.

o WDT reset: WDT expiration cause CPU to reset if enabled, otherwise interrupt.

o Core reset: Reset by the other CPU (e.g. N9 to reset CM4 or CM4 to reset N9).

o Wake-up from deep sleep mode: Reset by the MTCMOS power control.

2.4.10.4 Sleep/Wakeup sequence

The sleep/wakeup control sequence is shown in the diagram below.

Figure 2-10. Sleep/Wakeup Sequence

2.4.11

Memory Map

The table below describes how the peripherals are mapped to the CM4 memory.

When the MCU performs a read transaction to an undefined address, the bus returns 0. When the

MCU performs a write transaction to an undefined address, the bus regards it as an invalid

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