MT7697DN datasheet(23/84 Pages) ETC2

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MT7697D

Internet-of-Things Wireless Connectivity

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Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

The N9 subsystem and Cortex-M4 subsystem are in different clock domains, so the asynchronous

bridges are inserted in the bus fabric. N9 has the ability to (but would be rarely used) all the M4

peripherals.

2.4.4

Serial Flash Controller

MT7697D features a serial flash controller that can support the serial flash with the read mode of

(JEDEC) standard SPI mode, SPI-Quad mode, QPI (Quad Peripheral Interface) mode, Dual IO mode,

and Dual-Output mode.

The frequency of the serial clock rate is up to 64MHz. That provides 256Mbps equivalent throughput

on flash when SPI-quad mode or QPI mode is used.

Table 2-10. Flash Controller Support Read Mode

Read Mode

Description

SPI

1xIO for receiving command and address, 1xIO for output data

SPI-Quad

1xIO for receiving command, 4xIO for address, 4xIO for output data

QPI

4xIO for receiving command/address and output data

Dual-IO

1xIO for command, 2xIO for address and output data

Dual-Output

1xIO for receiving command, 2xIO for address and output data

The Serial Flash Controller Supports Two Operation Modes:



Direct read mode, which supports a high-throughput direct-access through AHB bus



Macro access mode, which supports flash access with arbitrary command and is through APB

bus.

2.4.5

DMA

Direct memory access (DMA) is used to transfer data between memory ↔ memory as well as

memory ↔ peripherals without MCU intervention.

2.4.5.1

DMA Functional Description

There are three types of DMA channels supported in MT7697D.



Full-size DMA: Both the source address and the destination address are programmable. It is

normally used for memory copy.



Half-size DMA: Either the source address or the destination address is programmable. It is

normally used for data movement between memory and peripherals.



Virtual FIFO DMA (VFF DMA): It is a half-size DMA with an additional FIFO control engine. It is

used to provide the buffering capacity for peripherals including UART.

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