Uniform Sector

Standard and Dual Serial Flash

GD25WD10C/05C

9

5. DATA PROTECTION

The GD25WD10C/05C provides the following data protection methods:

◆

Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will

reset to 0 in the following situations:

-Power-Up

-Write Disable (WRDI)

-Write Status Register (WRSR)

-Page Program (PP)

-Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)

◆

Software Protection Mode: The Block Protect (BP2, BP1, BP0) bits define the section of the protected memory area

which is read-only and unalterable.

◆

Hardware Protection Mode: WP# goes low to protect the BP0~BP2 bits and SRP bits.

◆

Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep

Power-Down Mode command.

◆

Write Inhibit Voltage (VWI): Device would reset automatically when VCC is below a certain threshold VWI.

Table1(a) GD25WD10C Protected area size

Status Register Content

Memory Content

BP2

BP1

BP0

Blocks

Addresses

Density

Portion

0

0

0

NONE

NONE

NONE

NONE

0

0

1

Sector 0 to 29

000000H-01DFFFH

120KB

Lower 30/32

0

1

0

Sector 0 to 27

000000H-01BFFFH

112KB

Lower 28/32

0

1

1

Sector 0 to 23

000000H-017FFFH

96KB

Lower 24/32

1

0

0

Sector 0 to 15

000000H-00FFFFH

64KB

Lower 16/32

1

0

1

All

000000H-01FFFFH

128KB

ALL

1

1

X

All

000000H-01FFFFH

128KB

ALL

Table1(b) GD25WD05C Protected area size

Status Register Content

Memory Content

BP2

BP1

BP0

Blocks

Addresses

Density

Portion

0

0

0

NONE

NONE

NONE

NONE

0

0

1

Sector 0 to 13

000000H-00DFFFH

56KB

Lower 14/16

0

1

0

Sector 0 to 11

000000H-00BFFFH

48KB

Lower 12/16

0

1

1

Sector 0 to 7

000000H-007FFFH

32KB

Lower 8/16

1

X

X

All

000000H-00FFFFH

64KB

ALL