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AD9929BBCZ 数据表(PDF) 13 Page - Analog Devices |
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AD9929BBCZ 数据表(HTML) 13 Page - Analog Devices |
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13 / 64 page ![]() AD9929 Rev. A | Page 13 of 64 Address Content Bit Width Default Value Register Name Register Description 0x1B (23:13) 11 – Unused (12:0) 13 0x1FFF XV3SPAT_TOG1 XV3SPAT Toggle Position #1 (Mode_A active) 0x1C (23:13)) 11 – Unused (12:0 13 0x1FFF XV3SPAT_TOG2 XV3SPAT Toggle Position #2 (Mode_A active) 0x1D (23:13) 11 – Unused (12:0) 13 0x1FFF XV4SPAT_TOG1 XV4SPAT Toggle Position #1 (Mode_A active) 0x1E (23:13) 11 – Unused (12:0) 13 0x1FFF XV4SPAT_TOG2 XV4SPAT Toggle Position #2 (Mode_A Active) 0x1F (23:13) 11 – Unused (12:0) 13 0x1FFF XV1SPAT_TOG1 XV1SPAT Toggle Position #1 (Mode_A Active) 0x20 (23:13) 11 – Unused (12:0) 13 0x1FFF XV1SPAT_TOG2 XV1SPAT Toggle Position #2 (Mode_B Active) 0x21 (23:13) 11 – Unused (12:0) 13 0x1FFF XV2SPAT_TOG1 XV2SPAT Toggle Position #1 (Mode_B Active) 0x22 (23:13) 11 – Unused (12:0) 13 0x1FFF XV2SPAT_TOG2 XV2SPAT Toggle Position #2 (Mode_B Active) 0x23 (23:13) 11 – Unused (12:0) 13 0x1FFF XV3SPAT_TOG1 XV3SPAT Toggle Position #1 (Mode_B Active) 0x24 (23:13) 11 – Unused (12:0) 13 0x1FFF XV3SPAT_TOG2 XV3SPAT Toggle Position #2 (Mode_B Active) 0x25 (23:13) 11 – Unused (12:0) 13 0x1FFF XV4SPAT_TOG1 XV4SPAT Toggle Position #1 (Mode_B Active) 0x26 (23:13) 11 – Unused (12:0) 13 0x1FFF XV4SPAT_TOG2 XV4SPAT Toggle Position #2 (Mode_B Active) 0xD5 (23:4) 20 0x00000 Unused 3 1 1 DCLK2SEL DCLK2 Selector (0 = Select Internal FD Signal To Be Output on FD/DCLK2 Pin 16, 1 = Select CLI To Be Output on FD/DCLK2 Pin 16) 2 1 0 DCLK1SEL DCLK1 Selector (0 = Select DLL Version for DCLK1 Output, 1 = Select CLI for DCLK1 Output) (1:0) 2 0 CLKDIV Input Clock Divider (0 = No Division, 1 = 1/2, 2 = 1/3, 3 = 1/4) 0xD6 (23:1) 23 0x000000 Unused 0 1 1 SLAVE_MODE Operating Mode ( 0 = Master Mode, 1 = Slave Mode) 1 This register defaults to VD synchronous mode type at power-up. VD sync type registers do not get updated until the first falling edge of VD is asserted after the register has been programmed. VD sync type registers can be programmed to be asynchronous registers by setting VDMODE = 1 (Address 0x01). |
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