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THCV236 数据表(PDF) 49 Page - California Eastern Labs |
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THCV236 数据表(HTML) 49 Page - California Eastern Labs |
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49 / 68 page  THCV235_THCV236_Rev.3.40_E Copyright©2016 THine Electronics, Inc. THine Electronics, Inc. 49/68 Security E Table 45. THCV236 Main-Link Control Register Map Address (Hex) Bit# R/W Default (Hex) Name Description Note Sub-Link Master Sub-Link Slave 0x50 0xD0 7 RW (*1) MAINMODE MAINMODE setting 0: V-by-One® HS Mode 1: Sync Free Mode - 6 RW (*1) HFSEL HFSEL setting 0: High Frequency Mode Disable 1: High Frequency Mode Enable - 5 RW 0 COL1 COL1 setting when MAINMODE =0 0: Color Space Converter Disable 1: Color Space Converter Enable when MAINMODE =1 Data Width Setting. See Table 20. - 4 RW (*1) COL0 COL0 setting Data Width Setting. See Table 20. - 3 RW 0 Reserved - 2:1 RW 0x0 Reserved - 0 RW 0 TTLDRV TTLDRV setting 0: Weak Drive Strength 1: Normal Drive Strength - 0x51 0xD1 7:6 R 0x0 Reserved - 5 RW 0 SSEN SSEN setting 0: SSCG Disable 1: SSCG Enable (*2) 4:0 RW 0x05 SPREAD SSCG modulation depth setting Spread depth = ±SPREAD x 0.1% (Center Spread) 0x52 0xD2 7:4 R 0x0 Reserved - 3:0 RW 0xD FMOD SSCG Modulation Frequency setting - 0x53 0xD3 7:2 R 0x00 Reserved - 1 RW 0 Reserved - 0 RW 0 BET_SEL Main-Link / Sub-Link Field BET Mode select 0: Main-Link Field BET Mode 1: Sub-Link Field BET Mode - 0x54 0xD4 7 R 0 Reserved - 6:0 RW 0x3E Reserved. Must be default setting. - 0x55 -0x6C 0xD5 -0xEC 7:0 RW 0x00 Reserved - 0x6D 0xED 7:3 R 0x00 Reserved - 2 RW 0 OUTSEL_ENABLE Permanent Clock Output Enable setting 0: Permanent Clock Output Disable 1: Permanent Clock Output Enable - 1:0 RW 0x1 OUTSEL_SETTING Permanent Clock Frequency setting 00: 80MHz (Clock Period : tOSC) 01: 40MHz (Clock Period : tOSC/2) 10: 20MHz (Clock Period : tOSC/4) 11: 10MHz (Clock Period : tOSC/8) (*3) 0x6E 0xEE 7:1 R 0x00 Reserved - 0 RW 1 Reserved. Must be 1 - 0x6F 0xEF 7:0 R 0x00 Reserved - 0x70 0xF0 7:2 R 0x00 Reserved - 1 RW 0 Reserved. Must be 0 - 0 RW 0 PLL_SET_EN SSCG PLL setting register Enable 1: Enable 0: Disable - 0x71 -0x75 0xF1 -0xF5 7:0 R 0x00 Reserved - 0x76 0xF6 7:6 R 0x0 Reserved - 5:0 RW 0xXX PLL_SET0 SSCG PLL setting (*4) 0x77 0xF7 7:4 R 0x0 Reserved - 3:0 RW 0x0 Reserved. Must be default setting. - 0x78 0xF8 7:0 RW 0xXX PLL_SET1 SSCG PLL setting (*4) 0x79 -0x7B 0xF9 -0xFB 7:0 RW 0x00 Reserved. Must be default setting. - 0x7C 0xFC 7:6 R 0x0 Reserved. - 5:0 RW 0xXX PLL_SET2 SSCG PLL setting (*4) 0x7D -0x7F 0xFD -0xFF 7:0 RW 0xXX Reserved. Must be default setting. - *1 Default value depends on RXDEFSEL setting when Power on sequence. RXDEFSEL=1 → default value is 0, RXDEFSEL=0 → default value is 1. *2 SSEN=1 and SPREAD=0 setting is forbidden. *3 Described value is typical value. It has variation in the range from min spec value to max spec value of tOSC. *4 See Table 11, Table 21. |
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