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THCV236 数据表(PDF) 13 Page - California Eastern Labs

部件名 THCV236
功能描述  SerDes transmitter and receiver with bi-directional transceiver
PDF  68 Pages
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制造商  CEL [California Eastern Labs]
网页  http://www.cel.com
标志 CEL - California Eastern Labs

THCV236 数据表(HTML) 13 Page - California Eastern Labs

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THCV235_THCV236_Rev.3.40_E
Copyright©2016 THine Electronics, Inc.
THine Electronics, Inc.
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Security E
Functional Overview
With High Speed CML SerDes, proprietary encoding scheme and CDR (Clock and Data Recovery)
architecture, the THCV235 and THCV236 enable transmission of 24/30bit video data, 2bits of user defined data,
synchronizing signals HSYNC,VSYNC and DE(Data Enable) as well as any data (up to 35 bit) through
Main-Link by single differential pair cable with minimal external components. In addition, the THCV235 and
THCV236 have Sub-Link which enables bi-directional transmission of 2-wire serial interface signals, GPIO
signals and also HTPDN/LOCKN signals for Main-Link through the other 1-pair of CML-Line. It does not need
any external frequency reference, such as a crystal oscillator. The THCV235 - THCV236 system is able to watch
and control peripheral devices via 2-wire serial interface or GPIOs. They also can report interrupt events caused
by change of GPIO inputs and internal statuses.
Functional Description
Internal Reference Output/Input Function (CAPOUT, CAPINA, CAPINP)
An internal regulator produces the 1.2V (CAPOUT). This 1.2V linear regulator can’t supply any other
external loads. Bypass CAPOUT to GND with 10uF.
CAPINP (THCV235 only) supplies reference voltage for internal PLL, and CAPINA supplies reference
voltage for any internal analog circuit. Bypass CAPINP/CAPINA to GND with 0.1uF to remove high frequency
noise. CAPOUT, CAPINA and CAPINP must be tied together.
Power supply AVDD is supposed to be stabilized with de-coupling capacitor and series noise filter (for example,
ferrite bead).
Figure 1. Connection of CAPOUT, CAPINA, CAPINP and Decoupling Capacitor
Power Down (PDN1, PDN0)
PDN1 and PDN0 turn off internal circuitry of Main-Link and Sub-Link separately.
Table 3. Power Down Setting
PDN1
PDN0
Operation
0
0
Both Main-Link and Sub-Link power down
0
1
Only Main-Link is active
1
0
Only Sub-Link is active
1
1
Both Main-Link and Sub-Link active



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