THCV236 datasheet(8/68 Pages) CEL

8 / 68 page

THCV235_THCV236_Rev.3.40_E

THine Electronics, Inc.

8/68

Security E

Table 1. Pin Sharing Description (THCV235)

Sub-Link State →

Sub-Link

Power Down

Low Speed Data

Bridge Mode

2-wire serial

I/F Mode

Sub-Link

Master/Slave →

Master

Slave

Master

Slave

PDN1

HTPDN/SUBMODE

LOCKN/MSSEL

BET/GPIO1

RF/BETOUT

BETOUT(*2)

COL0/INT/GPIO2

COL0

INT

GPIO2(*4)

COL1/SD0

COL1

SD0(input)

SD0(output)(*6)

SD0(SDA)

PRE/SD1

PRE

SD1(input)

SD1(output)(*6)

SD1(SCL)

CMLDRV/SD2/AIN0/GPIO3

CMLDRV

SD2(input)

SD2(output)(*6)

AIN0

GPIO3(*5)

LATEN/SD3/AIN1/GPIO4

-(*1)

SD3(output)(*6)

SD3(input)

AIN1

GPIO4(*5)

LATEN(*3)

SSEN/GPIO0

SSEN

GPIO0(*4)

BET/GPIO1

BET

GPIO1(*4)

MAINMODE/TCMP

MAINMODE

TCMP

HFSEL/TCMN

HFSEL

TCMN

LOCKN/MSSEL

LOCKN

MSSEL

HTPDN/SUBMODE

HTPDN

SUBMODE

*1 There is no function. LVCMOS IO has input state. Must be fixed at 0 or 1 input.

*2 When Field BET mode (Main-Link or Sub-Link), it functions as BETOUT output.

*3 When Field BET mode (Main-Link or Sub-Link), it functions as LATEN input.

*4 Programmable GPIO input is default on register setting.

*5 Through GPIO open-drain output is default on register setting.

*6 Low Speed Data Bridge Mode output is LVCMOS push pull buffer.

THCV236 数据表(PDF) 8 Page - California Eastern Labs

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