ADMV1013ACCZ-R7 datasheet(26/39 Pages) AD

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ADMV1013

Data Sheet

Rev. A | Page 26 of 39

CARRIER FEEDTHROUGH NULLING

Carrier feedthrough results from minute dc offsets that occur

on the internal mixer. In an I/Q modulator, nonzero differential

offsets mix with the LO and result in carrier feedthrough to the

RF output. In addition to this effect, some of the signal power at

the LO input couples directly to the RF output (this may be

because of the bond wire to bond wire coupling or coupling

through the silicon substrate). The net carrier feedthrough at

the RF output is the vector combination of the signals that appear

at the output because of these two effects.

The ADMV1013 offers, in IF mode, LO feedthrough offset

calibration adjustment in the LO path. Make these adjustments

through the MXER_OFF_ADJ_I_N bits (Register 0x07,

Bits[8:2], the MXER_OFF_ADJ_I_P bits (Register 0x07,

Bits[15:9]), the MXER_OFF_ADJ_Q_N bits (Register 0x08,

Bits[8:2]), and the MXER_OFF_ADJ_Q_P bits (Register 0x08,

Bits[15:9] in order to reject the unwanted LO signal.

For I/Q mode, the LO feedthrough offset amplitude and phase

calibration optimization can be adjusted externally through a

transceiver DAC.

ENVELOPE DETECTOR

The ADMV1013 features an envelope detector with a pseudo

differential voltage output. The envelope detector output pins

are VENV_P and VENV_N. The ADMV1013 turns on with the

envelope detector turned off. To turn on the envelope detector,

set the DET_EN bit (Bit 5, Register 0x03). The differential voltage

output of the envelope detector rises linearly to the square of

the input envelope voltage to the detector. The detector output

ranges from −45 dBm to −20 dBm when the input two tone

power ranges from −20 dBm to 0 dBm. The envelope detector

has 350 MHz, 3 dB envelope bandwidth and 1 GHz, 10 dB

envelope bandwidth. The envelope detector precedes the VVA

and the output driver of the ADMV1013.

POWER DOWN AND RESET

The SPI of the ADMV1013 allows the user to power down the

device circuits and reduce power consumption to typically 77 mW.

To turn off the entire chip, set the BG_PD bit (Register 0x03,

Bit 10) to 1. In addition, individual blocks of the circuit can be

powered down individually. To power down the quadrupler,

set the QUAD_PD bits (Register 0x03, Bits[13:11]) to 0x7. To

power down the VGA, set the VGA_PD bit (Register 0x03,

Bit 15) to 1. To power down the mixer, set the MIXER_PD bit

(Register 0x03, Bit 14) to 1. To power down the detector, set the

DET_EN bit (Register 0x03, Bit 5) to 0.

SERIAL PORT INTERFACE (SPI)

The SPI of the ADMV1013 allows the user to configure the device

for specific functions or operations via a 4-wire SPI port. This

interface provides users with added flexibility and customization.

The SPI consists of four control lines: SCLK, SDI, SDO, and

active low chip select lines, SEN/SEN2. SEN and SEN2 must be

connected together.

The ADMV1013 protocol consists of a write/read bit followed

by six register address bits, 16 data bits, and a parity bit. Both

the address and data fields are organized MSB first and end with

the LSB. For a write, set the first bit to 0. For a read, set the first

bit to 1.

The write cycle sampling must be performed on the rising edge.

The 16 bits of the serial write data are shifted in, MSB to lower

sideband. The ADMV1013 input logic level for the write cycle

supports a 1.8 V interface.

For a read cycle, up to 16 bits of serial read data are shifted out,

MSB first. After the 16 bits of data shift out, the parity bit shifts

out. The output logic level for a read cycle is 1.8 V.

The parity bit always follows the direction of the data. If parity

is not used, the transmitting end transmits zero instead of parity.

The parity is odd, which means that the total number of ones

transmitted during a command, including the read/write bit,

the address bit, the data bit, and the parity bit, must be odd.

Figure 82 and Figure 83 show the SPI write and read protocol,

respectively.

SCLK

SDI

D11

R/W

D15

D14

D13

D12

D10

SEN/SEN2

Figure 82. SPI Write Timing Diagram

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