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ADMV1013ACCZ-R7 数据表(PDF) 5 Page - Analog Devices |
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ADMV1013ACCZ-R7 数据表(HTML) 5 Page - Analog Devices |
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5 / 39 page  Data Sheet ADMV1013 Rev. A | Page 5 of 39 SERIAL PORT REGISTER TIMING Table 2. Parameter Description Min Typ Max Unit tSDI, SETUP Data to clock setup time 10 ns tSDI, HOLD Data to clock hold time 10 ns tSCLK, HIGH Clock high duration 40 to 60 % tSCLK, LOW Clock low duration 40 to 60 % tSCLK, SEN/SEN2_SETUP Clock to SEN/SEN2 setup time 30 ns tSCLK, DOT Clock to data out transition time 10 ns tSCLK, DOV Clock to data out valid time 10 ns tSCLK,SEN/SEN2_INACTIVE Clock to SEN/SEN2 inactive 20 ns t SEN/SEN2_INACTIVE Inactive SEN/SEN2 (between two operations) 80 ns Timing Diagram tSCLK, LOW tSCLK, DOT SDO tSCLK, DOV SDI tSDI, SETUP tSDI, HOLD SCLK tSCLK, HIGH tSCLK, SEN/SEN2_SETU P tSCLK, SEN/SEN2_INACTIVE tSEN/SEN2_INACTIVE SEN/SEN2 Figure 2. Serial Port Register Timing Diagram |
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