ADMV1014ACCZ-R7 datasheet(29/42 Pages) AD

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Data Sheet

ADMV1014

Rev. A | Page 29 of 42

IMAGE REJECTION DOWNCONVERSION

The ADMV1014 features the ability to downconvert to a real IF

output anywhere from 800 MHz to 6000 MHz, while suppressing

the unwanted image sideband by typically better than 30 dBc.

The IF outputs are quadrature to each other, 50 Ω single-ended,

and are internally ac coupled. IF_I and IF_Q are the quadrature IF

outputs. An external 90° hybrid is required to select the appropriate

sideband.

To configure the ADMV1014 in IF mode, set BB_AMP_PD

(Register 0x03, Bit 8) to 1 and set IF_AMP_PD (Register 0x03,

Bit 11) to 0

Each IF output features an amplifier with a digital attenuator.

The digital attenuator can be adjusted using fine or coarse steps.

The coarse steps for the IF_I can be adjusted using the IF_AMP_

COARSE_GAIN_I bit field (Register 0x08, Bits[11:8]). The coarse

steps for the IF_Q can be adjusted using the IF_AMP_COARSE_

GAIN_Q bit field (Register 0x09, Bits[15:12]). Each course gain

bit field has five settings. The fine steps for IF_I can be adjusted

using the IF_AMP_FINE_GAIN_I bit field (Register 0x08,

Bits[3:0]). The fine steps for the IF_Q can be adjusted using the

IF_AMP_FINE_GAIN_Q bit field (Register 0x08, Bits[7:4]).

Figure 77 to Figure 82 show the performance of these four bit

fields.

DETECTOR

The ADMV1014 features a square law detector that produces a

voltage linearly, according to the square of the RF voltage

output from the low noise amplifier. The detector can be

enabled by setting the DET_EN bit (Register 0x03, Bit 6) to 0. The

detector can be turned off by setting this bit to 1. The detector

linear range can be adjusted by setting the DET_PROG bit field

(Register 0x07, Bits[6:0]). These ranges are specified based on

the input power into the detector coming from the output of the

low noise amplifier. Each DET_PROG setting offers an

approximate 20 dB of ±1 dB dynamic range based on a two-

point linear regression from an ideal line for one temperature at

each DET_PROG setting. See Figure 89 to Figure 91 for more

performance information of the detector.

LO INPUT PATH

The LO input path operates from 5.4 GHz to 10.25 GHz with an

LO amplitude range of −6 dBm to +6 dBm. The LO has an

internal quadrupler (×4) and a programmable band-pass filter.

The LO band-pass filter is programmable using QUAD_FILTERS

(Register 0x04 Bits[3:0]). See the Performance at Different

Quad Filter Settings section for more information on the

QUAD_FILTERS settings.

The LO path can operate either differentially or single-ended

(SE). LOIP and LOIN are the inputs to the LO path. The LO

path can switch from differential to single-ended operation by

setting the QUAD_SE_MODE bits (Register 0x04, Bits[9:6]).

See the Performance Between Differential vs. Single-Ended LO

Input section for more information.

Figure 102 shows a block diagram of the LO path.

AMP

4 × LO_N

4 × LO_P

LO_N

LO_P

×4

Figure 102. LO Path Block Diagram

Enable the quadrupler by setting the QUAD_IBIAS_PD bit

(Register 0x03, Bit 7) to 0 and the QUAD_BG_PD bit

(Register 0x03, Bit 9) to 0. To power down the quadrupler, set

both of these bits to 1.

An unwanted image can be downconverted from the

quadrature error in generating the quadrature LO signals.

Deviation from ideal quadrature (that is, total image rejection

and no image tone is downconverted) on these signals limits the

amount of achievable image rejection.

The ADMV1014 offers about 25° of quadrature phase

adjustment in the LO path quadrature signals. Make these

adjustments through the LOAMP_PH_ADJ_I_FINE bits

(Register 0x05, Bits[15:9]) and the LOAMP_PH_ADJ_Q_FINE

(Register 0x05, Bits[8:2]) bits. These bits reject the unwanted

sideband signal. In IF mode amplitude adjustments can be made

to the complex outputs via IF_AMP_FINE_GAIN_Q

(Register 0x08, Bits[7:4]) and IF_AMP_FINE_GAIN_I

(Register 0x08, Bits[3:0]) to further reduce the unwanted

sideband.

POWER-DOWN

The SPI of the ADMV1014 allows the user to power down

device circuits and reduce power consumption. There are two

power-down modes: band gap power-down mode (BG_PD)

and individual power-down circuits mode. The BG_PD bit

(Register 0x03, Bit 5) and the QUAD_BG_PD bit (Register 0x03,

Bit 9) power down the band gap circuit. The QUAD_IBIAS_PD

bit (Register 0x03, Bit 7) and the IBIAS_PD bit (Register 0x03,

Bit 14) power down the specific circuits.

Table 7 shows the circuits that are controlled by their related

power-down bit, the typical power savings, and the latency

requirement to power the circuits back up.

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