ADMV1014ACCZ-R7 datasheet(30/42 Pages) AD

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ADMV1014

Data Sheet

Rev. A | Page 30 of 42

Table 7. Power-Down Power and Latency Requirements

Bit Name

Circuit

Typical Power

Savings (mW)

Power-Up

Latency (μs)

Power-Down

Latency (μs)

IBIAS_PD

Receiver bias current (IBIAS)

1172

QUAD_IBIAS_PD

LO path

238

BG_PD and QUAD_BG_PD

Band gap

1423

4.5

IBIAS_PD, IF_AMP_PD, QUAD_BG_PD,

BB_AMP_PD, QUAD_IBIAS_PD, BG_PD

Entire chip

1435

123456789

SCLK

SDI

D11

R/W

A5A4A3A2

D15

D14

D13

D12

D10

D9D8D7

D4D3D2D1D0

SEN

Figure 103. Write Serial Port Timing Diagram

1011

1415161718

192021222324

SCLK

SDI

SDO

D10

D9D8D7D6

D15D14D13D12D11

R/W

A4A3A2

SEN

Figure 104. Read Serial Port Timing Diagram

SERIAL PORT INTERFACE (SPI)

The SPI of the ADMV1014 allows the user to configure the device

for specific functions or operations via a 4-pin SPI port. This

interface provides users with added flexibility and customization.

The SPI consists of four control lines: SCLK, SDIN, SDO, and

SEN.

The ADMV1014 protocol consists of a write/read bit followed

by six register address bits, 16 data bits, and a parity bit. Both

the address and data fields are organized most significant bit

(MSB) first and end with the least significant bit. For a write, set

the first bit to 0. For a read, set the first bit to 1.

The write cycle sampling must be performed on the rising edge.

The 16 bits of the serial write data are shifted in, MSB to Lower

Sideband. The ADMV1014 input logic level for the write cycle

supports an 1.8 V interface.

For a read cycle, up to 16 bits of serial read data are shifted out,

MSB first. After the 16 bits of data shift out, the parity bit shifts

out. The output logic level for a read cycle is 1.8 V.

The parity bit always follows the direction of the data. If parity

is not used, the transmitting end transmits zero instead of parity.

The parity is odd, which means that the total number of ones

transmitted during a command, including the read/write bit,

the address bit, the data bit, and the parity bit, must be odd.

Figure 103 and Figure 104 show the SPI write and read

protocol, respectively.

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