STA450A datasheet(6/66 Pages) STMICROELECTRONICS

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STA450A

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Note 1. Guaranteed by Design

Note 2. Take into account 200 mV voltage drop in supply lines and Input/Output levels for frequency > 20MHz.

Note 3. Guaranteed by Ipu measurements

Note 4: Performed on all the input pins excluded the pull-down ones

Note 5: Performed on the I/O pins in tristate mode

1.0 FUNCTIONAL DESCRIPTION

1.1 PC BITSTREAM INTERFACE

The STA450A receives a serial data stream from the STA400A Channel Decoder via the PC Bitstream Inter-

face.

Figure 3 shows the stream format outputs from the CDEC (STA400A).

Figure 3. PC Bitstream Interface protocol

Table 1 shows the correspondence between CDEC output clock divider register and the data rate on the bus

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Vol

Low level output voltage 2)

Iol = 4mA

0.2

Voh

High level output voltage 2)

Ioh = 4mA

2.8

CIN

Input Capacitance 1)

1.2

COUT

Output Capacitance 1)

1.9

CIO

I/O (BiDir) Capacitance 1)

2.1

Ilatchup

I/O Latching Current

200

VESD

Electrostatic Protection

Leakage<1

µA4000

PCSD

PCDC

PCFS

432ms frame period

CLOCK

TSCC1

TSCC2

PRC_An

PRC_A1

PRC_B1

PRC_Zn

PRC_Z1

PRC_Bn

PCSD

PCDC

PCFS

DC ELECTRICAL CHARACTERISTCS (continued)

STA450A 数据表(PDF) 6 Page - STMicroelectronics

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