STA450A datasheet(9/66 Pages) STMICROELECTRONICS

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STA450A

N = pllsys_Nmodulo

M = pllsys_Mmodulo

The System PLL registers are configured through an indirection mechanism using the HOST_pll_add,

HOST_pll_data and HOST_pll_cmd registers; the HOST_pll_cmd register allows to update the control registers

of the PLL.

There are two levels of registers (Level 1 & Level 2). The first level of registers (Level 1) is configured through

the indirection mechanism. The second level of registers (Level 2) is a copy of the previous level in order to

update all the configuration bits at the same time. This mechanism avoids to have, during the configuration

phase, intermediate configurations that are not in line with the final desired configuration.

Assuming a 23.92MHz CLK input frequncy and CLK_M[1:0] = “11”, the default system frequency is 59.8MHz

See also the register description.

The Audio PLL

The "internal_pcmclk" of STA450A can be provided by two different sources: the Audio PLL or the OCLK port

of the chip.

The "m5" multiplexor and the direction of the OCLK tri-state port are configured by the register HOST_Pllpcm

(address 0x12).

An Audio PLL is embedded in STA450A.

The particularity of STA450A Audio PLL is the possibility to modify the Audio Sampling Frequency (LRCKT) in

steps of a few p.p.m. to compensate dynamically the audio sampling frequency offset between the receiver and

the broadcasting station; this compensation produces a jittering effect outside the audible range.

The STA450A receives from the STA400A (Channel Decoder) a dedicated signal every 432ms (PLL_SYNC)

and uses this signal to perform the audio sampling rate compensation; the control is done by the DSP core up-

dating the internal PLL registers.

Some PLL configuration registers are made available to the user to configure the PCM output according to the

used DAC.

The programmation for the desired Fs should be accomplished for both the Fs = 48KHz and Fs =

44.1KHz families before the start-up of the DSP (write in the register 0 x 4D)

The OCLK frequency can be derived from the following formula:

– X is the value of the HOST_APLL48_XDIV register (HOST_APLL441_XDIV) register.

– M is the value of the HOST_APLL48_MDIV register (HOST_APLL441_MDIV) register.

– N is the value of the HOST_APLL48_NDIV register (HOST_APLL441_NDIV) register.

– FRAC

the

decimal

value

the

concatenated

registers

HOST_APLL48_LSB

and

HOST_APLL48_MSB (HOST_APLL441_LSB and HOST_APLL441_MSB) as follows:

FRAC = 256 * HOST_APLL48_MSB + HOST_APLL48_LSB (= 256 * HOST_APLL441_MSB +

HOST_APLL441_LSB)

The changes in the registers are not effective once the DSP has been started.

OCLK_freq

-------------

23.92MHz

----------------------------

FRAC

65536

-----------------

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