STA450A datasheet(7/66 Pages) STMICROELECTRONICS

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STA450A

Table 1. Suggested CDEC clock divider/output rate correspondence.

The 432ms frame is divided in slots of 448 bytes; the minimum number af slots in a 432ms frame is 50, corre-

sponding to a Tslot of 8.64ms. The transmission is on bursts, whose duration can go from 299us up to 1.199ms

(refer to table 1) according to the clock divider factor selected in the STA400A.

An overview of the connection between the STA400A and the STA450A is given in Figure 4.

Figure 4. STA400A/STA450A Connection.

The synchronization process is started after a PCFS pulse is received through a Fast Interrupt port (pin 39). In

the case the PC Bitstream is stopped or the clock line is perturbed, the PCFS signal is used to reset the firmware

State Machine in the PC Bitsteam Interface (STA450A); this mechanism guarantees the start of the resync pro-

cess from a stable state.

The PC Bitstream Interface receives the data and fills the Header and the PC buffers; the Header buffer contains

the Header byte 1, the Header byte 2 and the Service preamble, the PC buffer contains the Payload channels

data.

1.2 STA450A Clocks Generation System

The STA450A Clocks generation System is shown in Figure 5: the 23.92MHz reference signal is entered in the

pin CLK_IN and is used to generate an internal system clock, with a System PLL, and an internal PCM clock,

with an Audio Fractional PLL .

A clock is made available at the output through the pin CLK_OUT.

MCLK (Hz)

Divider

F Out (Hz)

T Out (sec)

T Burst (sec)

23920000

11960000

8.361E-08

2.997E-04

5980000

1.672E-07

5.993E-04

3986667

2.508E-07

8.990E-04

2990000

3.344E-07

1.199E-03

CDEC

PCSD - DATA LINE

PCDC - CLOCK LINE

PCFS

TX/RX

SCLK

FAST IT

HEADER

BUFFER

SERVICE

LAYER

DSP

DECRYPT

BUFFER

AUDIO

BUFFER

DATA

BUFFER

FAST IT

MFP -PLL SYNC

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