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数据搜索系统，热门电子元器件搜索 |
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STA450A 数据表(PDF) 21 Page - STMicroelectronics |
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STA450A 数据表(HTML) 21 Page - STMicroelectronics |
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21 / 66 page  21/66 STA450A HOST_ClkStop Address : 0x3A Type : R Software Reset : NA Hardware Reset : 0 Description Clearing the bit 0 the clock to the core is started. HOST_SOFTVER Address : 0x40 Type : R/W Software Reset : NA Hardware Reset : NA Description The SOFTVER register is the version of the microcode which is running on the device (BCD). This register is updated just after a soft reset of the device. HOST_EVENTINTE 0 -1 -2 -3 Address : 0x44 - 0x41 Type : R/W Software Reset : NA Hardware Reset : NA Description These registers are associated to error condition inside the STA450A. The STA450A contains a 32 bits interrupt register associated with 32 bits enable register. A bit set in this register will enable the generation of an external interrupt on the interrupt line. The interrupt associated with each bit is given in the register INT description. HOST_EVENTINT 0 - 1 - 2 - 3 7654 3210 3A 7654 3210 40 7654 3210 44 INTE[31:24] 43 INTE[23:16] 42 INTE[15:8] 41 INTE[7:0] 7654 3210 48 INT[31:24] 47 INT[23:16] 46 INT[15:8] 45 INT[7:0] |
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