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56F8167 数据表(PDF) 158 Page - Freescale Semiconductor, Inc |
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56F8167 数据表(HTML) 158 Page - Freescale Semiconductor, Inc |
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158 / 184 page  56F8367 Technical Data, Rev. 7.0 158 Freescale Semiconductor Preliminary Figure 10-15 Quadrature Decoder Timing 10.13 Serial Communication Interface (SCI) Timing Figure 10-16 RXD Pulse Width Figure 10-17 TXD Pulse Width Table 10-21 SCI Timing1 1. Parameters listed are guaranteed by design. Characteristic Symbol Min Max Unit See Figure Baud Rate2 2. fMAX is the frequency of operation of the system clock, ZCLK, in MHz, which is 60MHz for the 56F8367 device , and 40MHz for the 56F8167 device. BR — (fMAX/16) Mbps — RXD3 Pulse Width 3. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1. RXDPW 0.965/BR 1.04/BR ns 10-16 TXD4 Pulse Width 4. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1. TXDPW 0.965/BR 1.04/BR ns 10-17 Phase B (Input) PIN PHL PHL Phase A (Input) PIN PHL PHL PPH PPH PPH PPH RXDPW RXD SCI receive data pin (Input) TXDPW TXD SCI receive data pin (Input) |
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