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56F8167 数据表(PDF) 157 Page - Freescale Semiconductor, Inc |
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56F8167 数据表(HTML) 157 Page - Freescale Semiconductor, Inc |
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157 / 184 page ![]() Quad Timer Timing 56F8367 Technical Data, Rev. 7.0 Freescale Semiconductor 157 Preliminary 10.11 Quad Timer Timing Figure 10-14 Timer Timing 10.12 Quadrature Decoder Timing Table 10-19 Timer Timing1, 2 1. In the formulas listed, T = the clock cycle. For 60MHz operation, T = 16.67ns. 2. Parameters listed are guaranteed by design. Characteristic Symbol Min Max Unit See Figure Timer input period PIN 2T + 6 — ns 10-14 Timer input high / low period PINHL 1T + 3 — ns 10-14 Timer output period POUT 1T - 3 — ns 10-14 Timer output high / low period POUTHL 0.5T - 3 — ns 10-14 Table 10-20 Quadrature Decoder Timing1, 2 1. In the formulas listed, T = the clock cycle. For 60MHz operation, T=16.67ns. 2. Parameters listed are guaranteed by design. Characteristic Symbol Min Max Unit See Figure Quadrature input period PIN 4T + 12 — ns 10-15 Quadrature input high / low period PHL 2T + 6 — ns 10-15 Quadrature phase period PPH 1T + 3 — ns 10-15 POUT POUTHL POUTHL PIN PINHL PINHL Timer Inputs Timer Outputs |
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