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56F8167 数据表(PDF) 153 Page - Freescale Semiconductor, Inc |
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56F8167 数据表(HTML) 153 Page - Freescale Semiconductor, Inc |
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153 / 184 page  Serial Peripheral Interface (SPI) Timing 56F8367 Technical Data, Rev. 7.0 Freescale Semiconductor 153 Preliminary Figure 10-8 Interrupt from Wait State Timing Figure 10-9 Recovery from Stop State Using Asynchronous Interrupt Timing 10.10 Serial Peripheral Interface (SPI) Timing Table 10-18 SPI Timing1 Characteristic Symbol Min Max Unit See Figure Cycle time Master Slave tC 50 50 — — ns ns 10-10, 10-11, 10-12, 10-13 Enable lead time Master Slave tELD — 25 — — ns ns 10-13 Enable lag time Master Slave tELG — 100 — — ns ns 10-13 Clock (SCK) high time Master Slave tCH 17.6 25 — — ns ns 10-10, 10-11, 10-12, 10-13 Clock (SCK) low time Master Slave tCL 24.1 25 — — ns ns 10-13 Instruction Fetch tIRI IRQA, IRQB First Interrupt Vector A0–A15, PS, DS, RD, WR Not IRQA Interrupt Vector tIW IRQA tIF A0–A15, PS, DS, RD, WR First Instruction Fetch |
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