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56F8167 数据表(PDF) 151 Page - Freescale Semiconductor, Inc |
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56F8167 数据表(HTML) 151 Page - Freescale Semiconductor, Inc |
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151 / 184 page  Reset, Stop, Wait, Mode Select, and Interrupt Timing 56F8367 Technical Data, Rev. 7.0 Freescale Semiconductor 151 Preliminary 10.9 Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2 1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and Stop modes), T = 125ns. 2. Parameters listed are guaranteed by design. Characteristic Symbol Typical Min Typical Max Unit See Figure RESET Assertion to Address, Data and Control Signals High Impedance tRAZ —21 ns 10-5 Minimum RESET Assertion Duration tRA 16T — ns 10-5 RESET Deassertion to First External Address Output3 3. During Power-On Reset, it is possible to use the device’s internal reset stretching circuitry to extend this period to 221T. tRDA 63T 64T ns 10-5 Edge-sensitive Interrupt Request Width tIRW 1.5T — ns 10-6 IRQA, IRQB Assertion to External Data Memory Access Out Valid, caused by first instruction execution in the interrupt service routine tIDM 18T — ns 10-7 tIDM - FAST 14T — IRQA, IRQB Assertion to General Purpose Output Valid, caused by first instruction execution in the interrupt service routine tIG 18T — ns 10-7 tIG - FAST 14T — Delay from IRQA Assertion (exiting Wait) to External Data Memory Access4 4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted. tIRI 22T — ns 10-8 tIRI -FAST 18T — Delay from IRQA Assertion to External Data Memory Access (exiting Stop) tIF 22T — ns 10-9 tIF - FAST 18T — IRQA Width Assertion to Recover from Stop State5 5. The interrupt instruction fetch is visible on the pins only in Mode 3. tIW 1.5T — ns 10-9 |
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