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56F8167 数据表(PDF) 159 Page - Freescale Semiconductor, Inc |
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56F8167 数据表(HTML) 159 Page - Freescale Semiconductor, Inc |
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159 / 184 page  Controller Area Network (CAN) Timing 56F8367 Technical Data, Rev. 7.0 Freescale Semiconductor 159 Preliminary 10.14 Controller Area Network (CAN) Timing Note: CAN is not available in the 56F8167 device. Figure 10-18 Bus Wakeup Detection 10.15 JTAG Timing Table 10-22 CAN Timing1 1. Parameters listed are guaranteed by design Characteristic Symbol Min Max Unit See Figure Baud Rate BRCAN — 1 Mbps — Bus Wake Up detection T WAKEUP 5 — µs 10-18 Table 10-23 JTAG Timing Characteristic Symbol Min Max Unit See Figure TCK frequency of operation using EOnCE1 1. TCK frequency of operation must be less than 1/8 the processor rate. fOP DC SYS_CLK/8 MHz 10-19 TCK frequency of operation not using EOnCE1 fOP DC SYS_CLK/4 MHz 10-19 TCK clock pulse width tPW 50 — ns 10-19 TMS, TDI data set-up time tDS 5— ns 10-20 TMS, TDI data hold time tDH 5— ns 10-20 TCK low to TDO data valid tDV —30 ns 10-20 TCK low to TDO tri-state tTS —30 ns 10-20 TRST assertion time tTRST 2T2 2. T = processor clock period (nominally 1/60MHz) —ns 10-21 T WAKEUP CAN_RX CAN receive data pin (Input) |
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