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VCBU68WMCE30 数据表(PDF) 29 Page - Texas Instruments |
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VCBU68WMCE30 数据表(HTML) 29 Page - Texas Instruments |
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29 / 208 page  TMS320DM368 www.ti.com SPRS668C – APRIL 2010 – REVISED JUNE 2011 Table 2-5. Pin Descriptions (continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State DDR_A5 V15 O DDR VDD18_DDR DDR Address Bus bit 05 DDR_A4 U15 O DDR VDD18_DDR DDR Address Bus bit 04 DDR_A3 T14 O DDR VDD18_DDR DDR Address Bus bit 03 DDR_A2 W15 O DDR VDD18_DDR DDR Address Bus bit 02 DDR_A1 V14 O DDR VDD18_DDR DDR Address Bus bit 01 DDR_A0 U14 O DDR VDD18_DDR DDR Address Bus bit 00 DDR_DQ15 V6 I/O DDR VDD18_DDR DDR Data Bus bit 15 DDR_DQ14 V7 I/O DDR VDD18_DDR DDR Data Bus bit 14 DDR_DQ13 R7 I/O DDR VDD18_DDR DDR Data Bus bit 13 DDR_DQ12 W7 I/O DDR VDD18_DDR DDR Data Bus bit 12 DDR_DQ11 V8 I/O DDR VDD18_DDR DDR Data Bus bit 11 DDR_DQ10 R8 I/O DDR VDD18_DDR DDR Data Bus bit 10 DDR_DQ9 U8 I/O DDR VDD18_DDR DDR Data Bus bit 09 DDR_DQ8 W8 I/O DDR VDD18_DDR DDR Data Bus bit 08 DDR_DQ7 R9 I/O DDR VDD18_DDR DDR Data Bus bit 07 DDR_DQ6 W9 I/O DDR VDD18_DDR DDR Data Bus bit 06 DDR_DQ5 V9 I/O DDR VDD18_DDR DDR Data Bus bit 05 DDR_DQ4 W10 I/O DDR VDD18_DDR DDR Data Bus bit 04 DDR_DQ3 V10 I/O DDR VDD18_DDR DDR Data Bus bit 03 DDR_DQ2 R10 I/O DDR VDD18_DDR DDR Data Bus bit 02 DDR_DQ1 V11 I/O DDR VDD18_DDR DDR Data Bus bit 01 DDR_DQ0 U11 I/O DDR VDD18_DDR DDR Data Bus bit 00 DDR_ T8 O DDR VDD18_DDR DDR: Loopback signal for external DQS gating. DQGATE0 Route to DDR and back to DDR_DQGATE1 with same constraints as used for DDR clock and data. DDR_ T9 I DDR VDD18_DDR DDR: Loopback signal for external DQS gating. DQGATE1 Route to DDR and back to DDR_DQGATE0 with same constraints as used for DDR clock and data. DDR_VREF P11 PWR DDR VDD18_DDR DDR: DDR_VREF is .5* VDD18_DDR = 0.9V for SSTL2 specific reference voltage. DDR_PADREFP R11 O DDR VDD18_DDR DDR: External resistor ( 50 ohm to ground) EM_A13 / GIO78 / V18 I/O/Z AEMIF / VDD_AEMIF1_18_ IPU/IPD Input Async EMIF: Address Bus bit[13] BTSEL[2] GIO / 33 disable BTSEL[ d by 2] default GIO: GIO[78] BTSEL[2]: See Section 3.2, Device Boot Modes for system usage of these pins. EM_A12 / GIO77 / U18 I/O/Z AEMIF / VDD_AEMIF1_18_ IPU/IPD Input Async EMIF: Address Bus bit[12] BTSEL[1] GIO / 33 disable BTSEL[ d by 1] default GIO: GIO[77] BTSEL[1]: See Section 3.2, Device Boot Modes for system usage of these pins. EM_A11 / GIO76 / V19 I/O/Z AEMIF / VDD_AEMIF1_18_ IPU/IPD Input Async EMIF: Address Bus bit[11] BTSEL[0] GIO / 33 disable BTSEL[ d by 0] default GIO: GIO[76] BTSEL[0]: See Section 3.2, Device Boot Modes for system usage of these pins. Copyright © 2010–2011, Texas Instruments Incorporated Device Overview 29 Submit Documentation Feedback Product Folder Link(s): TMS320DM368 |
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