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LP5550 数据表(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 LP5550
功能描述  PowerWise Technology Compliant Energy Management Unit
PDF  25 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

LP5550 数据表(HTML) 3 Page - National Semiconductor (TI)

  LP5550 Datasheet HTML 1Page - National Semiconductor (TI) LP5550 Datasheet HTML 2Page - National Semiconductor (TI) LP5550 Datasheet HTML 3Page - National Semiconductor (TI) LP5550 Datasheet HTML 4Page - National Semiconductor (TI) LP5550 Datasheet HTML 5Page - National Semiconductor (TI) LP5550 Datasheet HTML 6Page - National Semiconductor (TI) LP5550 Datasheet HTML 7Page - National Semiconductor (TI) LP5550 Datasheet HTML 8Page - National Semiconductor (TI) LP5550 Datasheet HTML 9Page - National Semiconductor (TI) Next Button
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Typical Application
Pin Descriptions
Pin #
Name
I/O
Type
Description
1
SCLK
I
D
PowerWise Interface (PWI) clock input
2
SPWI
I/O
D
PowerWise Interface (PWI) bi-directional data
3
RESETN
I
D
Reset, active low
4
VO2
O
A
LDO2 output, for supplying the I/O voltage on the SoC
5
VBAT1
P
P
Battery supply voltage
6
VO1
O
A
LDO1 output, for supplying a fixed voltage to a PLL etc. on the SoC
7
DGND
G
G
Digital ground
8
PWROK
O
D
Power OK, active high output signal
9
VBATSW
P
P
Battery supply voltage for switching regulator
10
SW
O
A
Switcher pin connected to coil
11
SWGND
G
G
Switcher ground
12
VBAT2
P
P
Battery supply voltage
13
VO3
O
A
LDO3 output, on-chip memory supply voltage
14
VFB
I
A
Switcher output voltage for supplying SoC core logic
15
AGND
G
G
Analog Ground
16
ENABLE
I
D
Enable, active high
A: Analog Pin
D: Digital Pin
I: Input Pin
O: Output Pin
I/O: Input/Output Pin
P: Power Pin
G: Ground Pin
20154530
FIGURE 4. Typical Application Circuit
www.national.com
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