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LP5550 数据表(PDF) 13 Page - National Semiconductor (TI) |
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LP5550 数据表(HTML) 13 Page - National Semiconductor (TI) |
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13 / 25 page ![]() Typical Performance Characteristics Unless otherwise stated: V IN=3.6V (Continued) Switch Current Limit vs. V IN Efficiency vs. Load (Switcher) 20154518 20154519 Switching Waveforms PWM Switching Waveforms PFM 20154520 20154521 LP5550 PWI Register Map The PWI standard supports sixteen 8-bit registers on the PWI slave. The table below summarizes these registers and shows default register bit values after reset. The following sub-sections provide additional detail on the use of each individual register. Summary Register Address Register Name Register Usage Type Reset Default Value 7654 3 2 1 0 0x0 R0 Core voltage R/W 0111 1 1 1 1 0x1 R1 Unused R/W ---- - - - - 0x2 R2 Memory retention voltage R/W 0110 0 - - - 0x3 R3 Status register R/O 0000 1 1 1 1 0x4 R4 PWI version number R/O 0000 0 0 0 1 0x5 R5 Unused R/W ---- - - - - 0x6 R6 Unused R/W ---- - - - - 0x7 R7 LDO2 voltage R/W 0111 1 - - - 0x8 R8 LDO1 voltage R/W 0010 1 - - - 0x9 R9 PFM/PWM force R/W 0 0 - - - - - - www.national.com 13 |
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