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OPA607 数据表(PDF) 32 Page - Texas Instruments

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部件名 OPA607
功能描述  OPA810 140-MHz, Rail-to-Rail Input/Output, FET-Input Operational Amplifier
PDF  50 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

OPA607 数据表(HTML) 32 Page - Texas Instruments

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background image
+
±
R
C
+
±
R
G
R
G
R
F
ADS911 0
18-bit
2 MSPS
R
S
+
±
R
C
-12V
-12V
12V
12V
-0.2V
12V
R
F
C
F
C
F
AV DD
DVDD
1.8V
1.8V
VIN+
VIN-
OPA 810
OPA 810
THS 456 1
+
±
C
CB
C
CB
5V
OPA 837
V
OCM
VREF
R
FIL T
C
FIL T
+
±
5V
OPA 378
REF505 0
5.0 V
Reference
12V
32
OPA810
SBOS799A – AUGUST 2019 – REVISED DECEMBER 2019
www.ti.com
Product Folder Links: OPA810
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
9.2.2 High-Z Input Data Acquisition Front-End
An ideal data acquisition system must measure a parameter without altering the measurand. When measuring a
voltage or current from sensors with a large output impedance, an extremely high input impedance front-end with
a pA range bias current is needed. Figure 76 shows an example circuit with the OPA810 used at the front-end.
For systems with large input voltage attenuated with the MΩ range resistor divider, the OPA810 with its pA range
bias currents adds negligible offset voltage and distortion because of the bias current induced resistor voltage
drops. This circuit shows a funneling architecture with the OPA810 FET-input amplifier used as a unity-gain
buffer, followed by attenuation to the ADS9110 5-V, full-scale input range and the ADC input drive using the
THS4561 fully-differential amplifier (FDA). The THS4561 helps achieve better SNR and ENOB than a similar 5-V
FDA, with a higher 12.6-V supply voltage and signal swings up to the ADC full-scale input range.
As a result of the capacitive switching and current inrush on the ADC VREF input pin, a wide bandwidth amplifier
such as the OPA837 is used with the OPA378 in a composite loop as a reference buffer. The OPA378, driven
from the REF5050 5-V voltage reference, offers high precision and the OPA837 gives fast-settling performance
for the ADC reference input drive. See the Reference Design Maximizing Signal Dynamic Range for True 10 Vpp
Differential Input to 20 bit ADC design guide for more a detailed analysis of this high-Z front-end.
Figure 76. High-Z Input Data Acquisition Front-End



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