OPA607 datasheet(10/50 Pages) TI1

10 / 50 page

OPA810

SBOS799A – AUGUST 2019 – REVISED DECEMBER 2019

www.ti.com

Product Folder Links: OPA810

Submit Documentation Feedback

Electrical Characteristics: 5 V (continued)

Test conditions unless otherwise noted: TA = 25°C, VS+ = 5 V, VS– = 0 V, common-mode voltage (VCM) = 1.25 V, RL = 1 kΩ

connected to 1.25 V

(1).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Test

Level(2)

(4)

Change in input offset from its value when input is biased to 0 V.

(5)

Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to

+PSRR and -PSRR.

Most positive input voltage

ΔVOS < 5 mV

(4)

VS+ + 0.2

VS+ + 0.3

Most negative input voltage

ΔVOS < 5 mV

(4)

VS- – 0.2

VS- – 0.3

Most positive input voltage

for main-JFET stage

See Figure 41

VS+ – 2.9

VS+ – 2.5

OUTPUT

VOCRH

Output voltage range high

RL = 667 Ω

VS+ – 0.12 VS+ – 0.09

TA = –40°C to +125°C, RLOAD = 667 Ω

VS+ – 0.15

VOCRL

Output voltage range low

RL = 667 Ω

VS–+ 0.06

VS– +

0.11

TA = –40°C to +125°C, RL = 667 Ω

VS– +

0.15

IO(max)

Linear output drive (sourcing

and sinking)

VO = 1.4 V, RL = 27.5 Ω, ΔVOS < 1

mV, VS+ = 3 V and VS– = –2 V

ISC

Output short-circuit current

Capacitive load drive

< 3-dB peaking, RS = 0 Ω

POWER SUPPLY

Quiescent current per

channel

3.15

3.7

4.5

PSRR

Power-supply rejection ratio

ΔVS = ±0.5 V

(5)

100

TA = –40°C to +125°C

AUXILIARY CMOS INPUT STAGE

Gain-bandwidth product

MHz

Input-referred voltage noise

f = 1 MHz

nV/

√Hz

Input offset voltage

VCM = VS+ – 1.5 V, no load

1.6

Input bias current

VCM = VS+ – 1.5 V

OPA607 数据表(PDF) 10 Page - Texas Instruments

OPA607 数据表(HTML) 10 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

数据表下载