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OPA607 数据表(PDF) 35 Page - Texas Instruments

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部件名 OPA607
功能描述  OPA810 140-MHz, Rail-to-Rail Input/Output, FET-Input Operational Amplifier
PDF  50 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

OPA607 数据表(HTML) 35 Page - Texas Instruments

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OPA810
www.ti.com
SBOS799A – AUGUST 2019 – REVISED DECEMBER 2019
Product Folder Links: OPA810
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Layout Guidelines (continued)
required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement
a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design
handbook for microstrip and stripline layout techniques). A 50-Ω environment is normally not necessary
onboard, and a higher impedance environment improves distortion. With a characteristic board trace
impedance defined based on board material and trace dimensions, a matching series resistor into the trace
from the output of the OPA810 is used as well as a terminating shunt resistor at the input of the destination
device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and
the input impedance of the destination device—this total effective impedance must be set to match the trace
impedance. If the 6-dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can
be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the
series resistor value to obtain sufficient phase margin and stability. This does not preserve signal integrity as
well as a doubly-terminated line. If the input impedance of the destination device is low, the signal attenuates
because of the voltage divider formed by the series output into the terminating impedance.
5. Take care to design the PCB layout for optimal thermal dissipation. For the extreme case of 125°C
operating ambient, using the approximate 134.8°C/W for the SOIC package, and an internal power of 24-V
supply × 4.7-mA 125°C supply current gives a maximum internal power dissipation of 113 mW. This power
gives a 15°C increase from ambient to junction temperature. Load power adds to this value and this
dissipation must also be calculated to determine the worst-case safe operating point.
6. Socketing a high-speed device such as the OPA810 is not recommended. The additional lead length
and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network
that can almost make achieving a smooth, stable frequency response impossible. Best results are obtained
by soldering the OPA810 onto the board.
11.1.1 Thermal Considerations
The OPA810 does not require heat sinking or airflow in most applications. Maximum allowed junction
temperature sets the maximum allowed internal power dissipation. Do not allow the maximum junction
temperature to exceed 150°C.
Operating junction temperature (TJ) is given by TA + PD × θJA. The total internal power dissipation (PD) is the sum
of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power.
Quiescent power is the specified no-load supply current times the total supply voltage across the part. PDL
depends on the required output signal and load but would, for a grounded resistive load, be at a maximum when
the output is fixed at a voltage equal to half of either supply voltage (for equal split-supplies). Under this condition
PDL = VS
2 / (4 × R
L) where RL includes feedback network loading.
The power in the output stage and not into the load that determines internal power dissipation.
As a worst-case example, compute the maximum TJ using a DCK (SC70 package) configured as a unity gain
buffer, operating on ±12-V supplies at an ambient temperature of 25°C and driving a grounded 500-Ω load.
PD = 24 V × 4.7 mA + 12
2 /(4 × 500 Ω) = 184.8 mW
Maximum TJ = 25°C + (0.185 W × 190.8°C/W) = 60°C, which is well below the maximum allowed junction
temperature of 150oC.



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