OPA607 datasheet(6/50 Pages) TI1

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OPA810

SBOS799A – AUGUST 2019 – REVISED DECEMBER 2019

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Electrical Characteristics: 10 V (continued)

Test conditions unless otherwise noted: TA = 25°C, VS+ = 5 V, VS– = –5 V, common-mode voltage (VCM) = mid-supply, RL = 1

kΩ connected to mid-supply

(1).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TEST

LEVEL(2)

(5)

Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to

+PSRR and –PSRR.

Most negative input voltage

ΔVOS < 5 mV

(4)

VS– – 0.2

VS– – 0.3

Most positive input voltage

for main-JFET stage

See Figure 17

VS+ – 2.9

VS+ – 2.5

OUTPUT

VOCRH

Output voltage range high

RL = 667 Ω

VS+ – 0.18 VS+ – 0.11

VOCRH

Output voltage range high

TA = –40°C to +125°C, RL = 667 Ω

VS+ – 0.2

VOCRL

Output voltage range low

RL = 667 Ω

VS– + 0.08

VS– +

0.15

VOCRL

Output voltage range low

TA = –40°C to +125°C, RL = 667 Ω

VS– + 0.2

IO(max)

Linear output drive (sourcing

and sinking)

VO = 2.65 V, RL = 51 Ω, ΔVOS < 1 mV

ISC

Output short-circuit current

100

Capacitive load drive

< 3-dB peaking, RS = 0 Ω

POWER SUPPLY

Quiescent current per

channel

3.7

4.6

PSRR

Power-supply rejection ratio

ΔVS = ±2 V

(5)

100

TA = –40°C to +125°C

AUXILIARY CMOS INPUT STAGE

Gain-bandwidth product

MHz

Input-referred voltage noise

f = 1 MHz

nV/

√Hz

Input offset voltage

VCM = VS+ – 1.5 V, no load

1.6

Input bias current

VCM = VS+ – 1.5 V

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