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STM32MP151AAB3 数据表(PDF) 184 Page - STMicroelectronics |
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STM32MP151AAB3 数据表(HTML) 184 Page - STMicroelectronics |
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184 / 253 page  Electrical characteristics STM32MP151A/D 184/253 DS12500 Rev 3 NAND controller waveforms and timings Figure 33 through Figure 36 represent synchronous waveforms, and Table 69 and Table 70 provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration: • FMC_SetupTime = 0x01 • FMC_WaitSetupTime = 0x03 • FMC_HoldSetupTime = 0x02 • FMC_HiZSetupTime = 0x01 • Bank = FMC_Bank_NAND • MemoryDataWidth = FMC_MemoryDataWidth_16b • ECC = FMC_ECC_Enable • ECCPageSize = FMC_ECCPageSize_512Bytes • TCLRSetupTime = 0 • TARSetupTime = 0 • CL = 30 pF In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period. Table 68. Synchronous non-multiplexed PSRAM write timings(1) Symbol Parameter Min Max Unit t(CLK) FMC_CLK period R×Tfmc_ker_ck -1(2) - ns td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 1 t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) R×Tfmc_ker_ck/2+0.5(2) - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 1 td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) R×Tfmc_ker_ck/2+1.5(2) - td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1 td(CLKH-NWEH) FMC_CLK high to FMC_NWE high R×Tfmc_ker_ck/2+0.5(2) - td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 3 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low 1 - td(CLKH-NBLH) FMC_CLK high to FMC_NBL high R×Tfmc_ker_ck/2+0.5(2) - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 3 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 1.5 - 1. Guaranteed by characterization results. 2. Clock ratio R = (FMC_CLK period / fmc_ker_ck period). |
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