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ST7DALI 数据表(PDF) 75 Page - STMicroelectronics |
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ST7DALI 数据表(HTML) 75 Page - STMicroelectronics |
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75 / 141 page  ST7DALI 75/141 DALI COMMUNICATION MODULE (Cont’d) In the example shown in Figure 44, the DCMC- SR[3:0] bits are updated automatically at each edge trigger (DALI signal change of phase). At the same time the value of the 4-bit sample clock counter is reset. By reading the DCMCSR[3:0] bits software can detect changes in the DALI signal pulse length. Figure 44. Example of DALI Signal Sampling DALI Signal Edge Trigger tCPU tCPU tCPU 4-bit sample clock counter (/16 divider) 0000 0001 1111 0000 xxxx 0000 0000 1111 xxxx DCMCSR[3:0] bits tCPU= f CPU m 1 m = (DCMCLK integer value+1) x tCPU fDALI= 1.2 kHz N = 207 (DCMCLK) fCPU= 8 MHz tCPU = 125ns m = 26 µs (208 x 125ns) Example: Legend: 833.33µs 1 |
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